Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Scheda Tecnica
Codici prodotto
AT32UC3L0-XPLD
106
32099G–06/2011
AT32UC3L016/32/64
11.4
Rev. D - 06/2010
11.5
Rev. C - 06/2010
11.6
Rev. B - 05/2010
13.
TC: Added features and version register.
14.
SAU: Added OPEN bit to config register. Added description of unlock fields.
15.
TWIS: SCR is Write-only. Improved explanation of slave transmitter mode. Updated data
transfer diagrams.
transfer diagrams.
16.
Electrical Characteristics: Added more values. Added notes on simulated and characterized
values. Added pin capacitance, rise, and fall times. Added timing characteristics. Removed all
TBDs. Added ADC analog input characteristics. Symbol cleanup.
values. Added pin capacitance, rise, and fall times. Added timing characteristics. Removed all
TBDs. Added ADC analog input characteristics. Symbol cleanup.
17.
Errata: Updated errata list.
1.
Ordering Information: Ordering code for TQFP ES changed from AT32UC3L064-AUES to
AT32UC3L064-AUTES. TLLGA48 Tray option added.
AT32UC3L064-AUTES. TLLGA48 Tray option added.
1.
Features and Description: Added QTouch library support.
2.
USART: Description of unimplemented features removed.
3.
Electrical Characteristics: Power Consumption numbers updated. Flash timing numbers
added.
added.
1.
Package and Pinout: Added pinout figure for TLLGA48 package.
2.
Package and Pinout, GPIO function multiplexing:TWIMS0-TWCK on PA20 removed. ADCIFB-
AD[3] on PA17 removed, number of ADC channels are 8, not 9.
AD[3] on PA17 removed, number of ADC channels are 8, not 9.
3.
I/O Lines Considerations: Added: Following pins have high-drive capability: PA02, PA06,
PA08, PA09, and PB01.
PA08, PA09, and PB01.
Some TWI0 pins are SMBUS compliant (PA21, PB04, PB05).
4.
HMATRIX Masters: PDCA is master 4, not master 3. SAU is master 3, not master 4.
5.
SAU: IDLE bit added in the Status Register.
6.
PDCA: Number of PDCA performance monitors is device dependent.
7.
Peripheral Event System: Chapter updated.
8.
PM: Bits in RCAUSE registers removed and renamed (JTAGHARD and AWIREHARD renamed
to JTAG and AWIRE respectively, JTAG and AWIRE removed. BOD33 bit removed).
to JTAG and AWIRE respectively, JTAG and AWIRE removed. BOD33 bit removed).
9.
PM: RCAUSE.BOD33 bit removed. SM33 reset will be detected as a POR reset.
10.
PM: WDT can be used as wake-up source if WDT is clocked from 32KHz oscillator.
11.
PM: Entering Shutdown mode description updated.
12.
SCIF: DFLL output frequency is 40-150MHz, not 20-150MHz or 30-150MHz.