Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Scheda Tecnica

32099G–06/2011

Notes:

1. Spread Spectrum Generator (SSG) is disabled by writing a zero to the EN bit in the SCIF.DFLL0SSG register.
2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

Digital Frequency Locked Loop Characteristics

f

OUT

Output frequency

40

150

MHz

f

REF

Reference frequency

8

150

kHz

FINE resolution

FINE > 100, all COARSE values

0.25

%

Frequency drift over voltage 
and temperature

See 

Accuracy

Fine lock, f

REF

 = 32kHz, SSG disabled

0.1

0.5

%

Accurate lock, f

REF 

= 32kHz, dither clk 

RCSYS/2, SSG disabled

0.06

0.5

Fine lock, f

REF 

= 8-150kHz, SSG 

disabled

0.2

1

Accurate lock, f

REF

 = 8-150kHz, dither 

clk RCSYS/2, SSG disabled

0.1

1

I

DFLL

Power consumption

22

µA/MHz

t

STARTUP

Startup time

Within 90% of final values

100

µs

t

LOCK

Lock time

f

REF 

= 32kHz, fine lock, SSG disabled

600

f

REF 

= 32kHz, accurate lock, dithering 

clock = RCSYS/2, SSG disabled

1100