Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Scheda Tecnica
Codici prodotto
AT32UC3L0-XPLD
68
32099G–06/2011
AT32UC3L016/32/64
Note:
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
Maximum SPI Frequency, Master Output
The maximum SPI master output frequency is given by the following formula:
Where
is the MOSI delay, SPI2 or SPI5 depending on CPOL and NCPHA.
is the
maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the
maximum frequency of the pins.
maximum frequency of the pins.
Maximum SPI Frequency, Master Input
The maximum SPI master input frequency is given by the following formula:
Where
is the MISO setup and hold time, SPI0 + SPI1 or SPI3 + SPI4 depending on
CPOL and NCPHA.
is the SPI slave response time. Please refer to the SPI slave
datasheet for
.
7.10.4.2
Slave mode
Figure 7-15. SPI Slave Mode With (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)
Table 7-40.
SPI Timing, Master Mode
Symbol
Parameter
Conditions
Min
Max
Units
SPI0
MISO setup time before SPCK rises
V
VDDIO
from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
28.4 + (t
CLK_SPI
)/2
ns
SPI1
MISO hold time after SPCK rises
0
SPI2
SPCK rising to MOSI delay
7.1
SPI3
MISO setup time before SPCK falls
22.8 + (t
CLK_SPI
)/2
SPI4
MISO hold time after SPCK falls
0
SPI5
SPCK falling to MOSI delay
11.0
f
SPCKMAX
MIN f
PINMAX
1
SPIn
------------
(
,
)
=
SPIn
f
PINMAX
f
SPCKMAX
1
SPIn t
VALID
+
------------------------------------
=
SPIn
t
VALID
t
VALID
SPI7
SPI8
MISO
SPCK
MOSI
SPI6