Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Scheda Tecnica
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AT91SAM9N12-EK
Coprocessor Interface
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
8-5
If a coprocessor instruction busy-waits then CPPASS is asserted on every cycle until
the coprocessor instruction is executed. If an interrupt occurs during busy-waiting then
CPPASS is driven LOW and the coprocessor should stop the coprocessor instruction
execution.
the coprocessor instruction is executed. If an interrupt occurs during busy-waiting then
CPPASS is driven LOW and the coprocessor should stop the coprocessor instruction
execution.
Another output, CPLATECANCEL is used to cancel a coprocessor instruction when
the instruction preceding it caused a Data Abort. This is valid on the rising edge of CLK
on the cycle after the first coprocessor Execute cycle of a coprocessor instruction.
the instruction preceding it caused a Data Abort. This is valid on the rising edge of CLK
on the cycle after the first coprocessor Execute cycle of a coprocessor instruction.
On the rising edge of the clock the ARM9EJ-S core examines the coprocessor
handshake signals CHSDE[1:0] and CHSEX[1:0]:
handshake signals CHSDE[1:0] and CHSEX[1:0]:
•
if a new instruction is entering the Execute stage in the next cycle, then it
examines CHSDE[1:0]
examines CHSDE[1:0]
•
if the coprocessor instruction currently in Execute requires another Execute cycle,
then it examines CHSEX[1:0].
then it examines CHSEX[1:0].
The handshake signals encode one of four states, as shown in Table 8-1.
Table 8-1 Handshake signal encoding
State
Value
Description
WAIT
00
If there is a coprocessor attached that can handle the instruction, but not immediately, then the
coprocessor handshake signals are driven to indicate that the ARM9EJ-S core has stalled. This is
known as the busy-wait condition. In the busy-wait condition, the ARM9EJ-S core loops in an idle
state waiting for CHSEX[1:0] to be driven to another state, or for an interrupt to occur. If
CHSEX[1:0] changes to ABSENT then the undefined instruction trap is taken. If CHSEX[1:0]
changes to GO or LAST then the instruction proceeds as described in GO. If an interrupt occurs
then the ARM9EJ-S core is forced out of the busy-wait state. This is indicated to the coprocessor
by the CPPASS signal going LOW. When the instruction is restarted the coprocessor must not
commit to the instruction (that is, change any of the coprocessor state) until the coprocessor has
seen CPPASS HIGH when the handshake signals indicate the GO or LAST condition.
coprocessor handshake signals are driven to indicate that the ARM9EJ-S core has stalled. This is
known as the busy-wait condition. In the busy-wait condition, the ARM9EJ-S core loops in an idle
state waiting for CHSEX[1:0] to be driven to another state, or for an interrupt to occur. If
CHSEX[1:0] changes to ABSENT then the undefined instruction trap is taken. If CHSEX[1:0]
changes to GO or LAST then the instruction proceeds as described in GO. If an interrupt occurs
then the ARM9EJ-S core is forced out of the busy-wait state. This is indicated to the coprocessor
by the CPPASS signal going LOW. When the instruction is restarted the coprocessor must not
commit to the instruction (that is, change any of the coprocessor state) until the coprocessor has
seen CPPASS HIGH when the handshake signals indicate the GO or LAST condition.
GO
01
The GO state indicates that the coprocessor can execute the instruction immediately, and that it
requires another cycle of execution. Both the ARM9EJ-S core and the coprocessor must consider
the state of the CPPASS signal before committing to the instruction. For an LDC or STC
instruction, then the coprocessor instruction drives the handshake signals with GO when two or
more words still have to be transferred. When only one further word is required the coprocessor
drives the handshake signals with LAST.
requires another cycle of execution. Both the ARM9EJ-S core and the coprocessor must consider
the state of the CPPASS signal before committing to the instruction. For an LDC or STC
instruction, then the coprocessor instruction drives the handshake signals with GO when two or
more words still have to be transferred. When only one further word is required the coprocessor
drives the handshake signals with LAST.
ABSENT
10
If there is no coprocessor attached that can execute the coprocessor instruction, then the handshake
signals indicate the ABSENT state and the ARM9EJ-S core takes the undefined instruction trap.
signals indicate the ABSENT state and the ARM9EJ-S core takes the undefined instruction trap.
LAST
11
An LDC or STC instruction might transfer more than one word of data. If this is the case then,
possibly after busy waiting, the coprocessor drives the coprocessor handshake signals with a
number of GO states, followed by a LAST cycle. The LAST indicates that the next transfer is the
final one. If there was only one transfer then the sequence would be [WAIT,[WAIT,...]],LAST.
possibly after busy waiting, the coprocessor drives the coprocessor handshake signals with a
number of GO states, followed by a LAST cycle. The LAST indicates that the next transfer is the
final one. If there was only one transfer then the sequence would be [WAIT,[WAIT,...]],LAST.