Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Scheda Tecnica
Codici prodotto
AT91SAM9G25-EK
120
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
14.4.6 Reset Controller Status Register
The Reset Controller status register (RSTC_SR) provides several status fields:
z
RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
z
SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset
should be performed until the end of the current one. This bit is automatically cleared at the end of the current
software reset.
should be performed until the end of the current one. This bit is automatically cleared at the end of the current
software reset.
z
NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising
edge.
edge.
z
URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is
also detected on the Master Clock (MCK) rising edge (see
also detected on the Master Clock (MCK) rising edge (see
resets the URSTS bit.
Figure 14-9. Reset Controller Status and Interrupt
MCK
NRST
NRSTL
2 cycle
resynchronization
2 cycle
resynchronization
URSTS
read
RSTC_SR
Peripheral Access
rstc_irq
if (URSTEN = 0) and
(URSTIEN = 1)