Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Scheda Tecnica
Codici prodotto
AT91SAM9G25-EK
219
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
23.5.1 Pull-up and Pull-down Resistor Control
Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resistor. The pull-up resistor
can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable
Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status
Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled. The
pull-down resistor can be enabled or disabled by writing respectively PIO_PPDER (Pull-down Enable Register) and
PIO_PPDDR (Pull-down Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in
PIO_PPDSR (Pull-down Status Register). Reading a 1 in PIO_PPDSR means the pull-up is disabled and reading a 0
means the pull-down is enabled.
can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable
Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status
Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled. The
pull-down resistor can be enabled or disabled by writing respectively PIO_PPDER (Pull-down Enable Register) and
PIO_PPDDR (Pull-down Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in
PIO_PPDSR (Pull-down Status Register). Reading a 1 in PIO_PPDSR means the pull-up is disabled and reading a 0
means the pull-down is enabled.
Enabling the pull-down resistor while the pull-up resistor is still enabled is not possible. In this case, the write of
PIO_PPDER for the concerned I/O line is discarded. Likewise, enabling the pull-up resistor while the pull-down resistor is
still enabled is not possible. In this case, the write of PIO_PUER for the concerned I/O line is discarded.
PIO_PPDER for the concerned I/O line is discarded. Likewise, enabling the pull-up resistor while the pull-down resistor is
still enabled is not possible. In this case, the write of PIO_PUER for the concerned I/O line is discarded.
Control of the pull-up resistor is possible regardless of the configuration of the I/O line.
After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0, and all the pull-downs are disabled,
i.e. PIO_PPDSR resets at the value 0xFFFFFFFF.
i.e. PIO_PPDSR resets at the value 0xFFFFFFFF.
23.5.2 I/O Line or Peripheral Function Selection
When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers PIO_PER
(PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of
the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO
Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the
PIO_ABCDSR1 and PIO_ABCDSR2 (ABCD Select Registers). A value of 1 indicates the pin is controlled by the PIO
controller.
(PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of
the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO
Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the
PIO_ABCDSR1 and PIO_ABCDSR2 (ABCD Select Registers). A value of 1 indicates the pin is controlled by the PIO
controller.
If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have
no effect and PIO_PSR returns 1 for the corresponding bit.
no effect and PIO_PSR returns 1 for the corresponding bit.
After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in some
events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must
be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus,
the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device.
events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must
be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus,
the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device.
23.5.3 Peripheral A or B or C or D Selection
The PIO Controller provides multiplexing of up to four peripheral functions on a single pin. The selection is performed by
writing PIO_ABCDSR1 and PIO_ABCDSR2 (ABCD Select Registers).
writing PIO_ABCDSR1 and PIO_ABCDSR2 (ABCD Select Registers).
For each pin:
z
The corresponding bit at level 0 in PIO_ABCDSR1 and the corresponding bit at level 0 in PIO_ABCDSR2 means
peripheral A is selected.
peripheral A is selected.
z
The corresponding bit at level 1 in PIO_ABCDSR1 and the corresponding bit at level 0 in PIO_ABCDSR2 means
peripheral B is selected.
peripheral B is selected.
z
The corresponding bit at level 0 in PIO_ABCDSR1 and the corresponding bit at level 1 in PIO_ABCDSR2 means
peripheral C is selected.
peripheral C is selected.
z
The corresponding bit at level 1 in PIO_ABCDSR1 and the corresponding bit at level 1 in PIO_ABCDSR2 means
peripheral D is selected.
peripheral D is selected.
Note that multiplexing of peripheral lines A, B, C and D only affects the output line. The peripheral input lines are always
connected to the pin input.
connected to the pin input.
Writing in PIO_ABCDSR1 and PIO_ABCDSR2 manages the multiplexing regardless of the configuration of the pin.
However, assignment of a pin to a peripheral function requires a write in the peripheral selection registers
(PIO_ABCDSR1 and PIO_ABCDSR2) in addition to a write in PIO_PDR.
However, assignment of a pin to a peripheral function requires a write in the peripheral selection registers
(PIO_ABCDSR1 and PIO_ABCDSR2) in addition to a write in PIO_PDR.
After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are 0, thus indicating that all the PIO lines are configured on peripheral
A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode.
A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode.