Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Scheda Tecnica

Codici prodotto

AT91SAM9G25-EK

576

SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

32.7.23 UDPHS DMA Channel Address Register

Name:

UDPHS_DMAADDRESSx [x = 0..5]

Address:

0xF803C304 [0], 0xF803C314 [1], 0xF803C324 [2], 0xF803C334 [3], 0xF803C344 [4], 0xF803C354 [5]

Access:

Read-write

Note:

Channel 0 is not used.

• BUFF_ADD: Buffer Address

This field determines the AHB bus starting address of a DMA channel transfer.

Channel start and end addresses may be aligned on any byte boundary.

The firmware may write this field only when the UDPHS_DMASTATUS register CHANN_ENB bit is clear.

This field is updated at the end of the address phase of the current access to the AHB bus. It is incrementing of the access byte
width. The access width is 4 bytes (or less) at packet start or end, if the start or end address is not aligned on a word boundary.

The packet start address is either the channel start address or the next channel address to be accessed in the channel buffer.

The packet end address is either the channel end address or the latest channel address accessed in the channel buffer.

The channel start address is written by software or loaded from the descriptor, whereas the channel end address is either deter-
mined by the end of buffer or the UDPHS device, USB end of transfer if the UDPHS_DMACONTROLx register END_TR_EN bit is
set.

BUFF_ADD