Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Scheda Tecnica
Codici prodotto
AT91SAM9G25-EK
940
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
• FSDEN: Frame Sync Data Enable
0 = The TD line is driven with the default value during the Transmit Frame Sync signal.
1 = SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
• FSEDGE: Frame Sync Edge Detection
Determines which edge on frame sync will generate the interrupt TXSYN (Status Register).
• FSLEN_EXT: FSLEN Field Extension
Extends FSLEN field. For details, refer to FSLEN bit description on
3
LOW
TF pin Driven Low during data transfer
4
HIGH
TF pin Driven High during data transfer
5
TOGGLING
TF pin Toggles at each start of data transfer
Value
Name
Description
0
POSITIVE
Positive Edge Detection
1
NEGATIVE
Negative Edge Detection
Value
Name
Description