Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Scheda Tecnica
Codici prodotto
ATSAM4E-XPRO
1223
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
RTY: Retry Test
Must be set to zero for normal operation. If set to one the backoff between collisions will always be one slot time. Setting
this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counter's
decrement time from 512 bit times, to every GRXCK cycle.
this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counter's
decrement time from 512 bit times, to every GRXCK cycle.
PEN: Pause Enable
When set, transmission will pause if a non-zero 802.3 classic pause frame is received and PFC has not been negotiated.
RXBUFO: Receive Buffer Offset
Indicates the number of bytes by which the received data is offset from the start of the receive buffer
LFERD: Length Field Error Frame Discard
Setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and
14 in a non-VLAN tagged frame) to be discarded. This only applies to frames with a length field less than 0x0600.
14 in a non-VLAN tagged frame) to be discarded. This only applies to frames with a length field less than 0x0600.
RFCS: Remove FCS
Setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The
frame length indicated will be reduced by four bytes in this mode.
frame length indicated will be reduced by four bytes in this mode.
CLK: MDC CLock Division
Set according to MCK speed. These three bits determine the number MCK will be divided by to generate Management
Data Clock (MDC). For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz (MDC is only active dur-
ing MDIO read and write operations).
Data Clock (MDC). For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz (MDC is only active dur-
ing MDIO read and write operations).
DBW: Data Bus Width
Should always be written to 0.
DCPF: Disable Copy of Pause Frames
Set to one to prevent valid pause frames being copied to memory. When set, pause frames are not copied to memory
regardless of the state of the Copy All Frames bit, whether a hash match is found or whether a type ID match is identified.
If a destination address match is found, the pause frame will be copied to memory. Note that valid pause frames received
will still increment pause statistics and pause the transmission of frames as required.
regardless of the state of the Copy All Frames bit, whether a hash match is found or whether a type ID match is identified.
If a destination address match is found, the pause frame will be copied to memory. Note that valid pause frames received
will still increment pause statistics and pause the transmission of frames as required.
RXCOEN: Receive Checksum Offload Enable
When set, the receive checksum engine is enabled. Frames with bad IP, TCP or UDP checksums are discarded.
EFRHD: Enable Frames Received in Half Duplex
Enable frames to be received in half-duplex mode while transmitting.
Value
Name
Description
0
MCK_8
MCK divided by 8 (MCK up to 20 MHz)
1
MCK_16
MCK divided by 16 (MCK up to 40 MHz)
2
MCK_32
MCK divided by 32 (MCK up to 80 MHz)
3
MCK_48
MCK divided by 48 (MCK up to 120 MHz)
4
MCK_64
MCK divided by 64 (MCK up to 160 MHz)
5
MCK_96
MCK divided by 96 (MCK up to 240 MHz)