Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Scheda Tecnica
Codici prodotto
ATSAM4E-XPRO
719
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
Figure 34-4.
Output Line Timings
34.5.8 Inputs
The level on each I/O line can be read through PIO_PDSR. This register indicates the level of the I/O lines
regardless of their configuration, whether uniquely as an input, or driven by the PIO Controller, or driven by a
peripheral.
regardless of their configuration, whether uniquely as an input, or driven by the PIO Controller, or driven by a
peripheral.
Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the
levels present on the I/O line at the time the clock was disabled.
levels present on the I/O line at the time the clock was disabled.
34.5.9 Input Glitch and Debouncing Filters
Optional input glitch and debouncing filters are independently programmable on each I/O line.
The glitch filter can filter a glitch with a duration of less than 1/2 peripheral clock and the debouncing filter can filter
a pulse of less than 1/2 period of a programmable divided slow clock.
a pulse of less than 1/2 period of a programmable divided slow clock.
The selection between glitch filtering or debounce filtering is done by writing in the PIO Input Filter Slow Clock
Disable register (PIO_IFSCDR) and the PIO Input Filter Slow Clock Enable register (PIO_IFSCER). Writing
PIO_IFSCDR and PIO_IFSCER, respectively, sets and clears bits in the Input Filter Slow Clock Status register
(PIO_IFSCSR).
Disable register (PIO_IFSCDR) and the PIO Input Filter Slow Clock Enable register (PIO_IFSCER). Writing
PIO_IFSCDR and PIO_IFSCER, respectively, sets and clears bits in the Input Filter Slow Clock Status register
(PIO_IFSCSR).
The current selection status can be checked by reading the register PIO_IFSCSR.
If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 master clock period.
If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2 programmable
divided slow clock period.
divided slow clock period.
For the debouncing filter, the period of the divided slow clock is performed by writing in the DIV field of the Slow
Clock Divider register (PIO_SCDR).
Clock Divider register (PIO_SCDR).
t
div_slclk
= ((DIV + 1)
× 2) × t
slow_clock
When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 selected clock
cycle (selected clock represents peripheral clock or divided slow clock depending on PIO_IFSCDR and
PIO_IFSCER programming) is automatically rejected, while a pulse with a duration of one selected clock
(peripheral clock or divided slow clock) cycle or more is accepted. For pulse durations between 1/2 selected clock
cycle and one selected clock cycle, the pulse may or may not be taken into account, depending on the precise
timing of its occurrence. Thus for a pulse to be visible, it must exceed one selected clock cycle, whereas for a glitch
to be reliably filtered out, its duration must not exceed 1/2 selected clock cycle.
cycle (selected clock represents peripheral clock or divided slow clock depending on PIO_IFSCDR and
PIO_IFSCER programming) is automatically rejected, while a pulse with a duration of one selected clock
(peripheral clock or divided slow clock) cycle or more is accepted. For pulse durations between 1/2 selected clock
cycle and one selected clock cycle, the pulse may or may not be taken into account, depending on the precise
timing of its occurrence. Thus for a pulse to be visible, it must exceed one selected clock cycle, whereas for a glitch
to be reliably filtered out, its duration must not exceed 1/2 selected clock cycle.
The filters also introduce some latencies, illustrated in
and
.
2 cycles
APB Access
2 cycles
APB Access
Peripheral clock
Write PIO_SODR
Write PIO_ODSR at 1
PIO_ODSR
PIO_PDSR
Write PIO_CODR
Write PIO_ODSR at 0