Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Scheda Tecnica

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

4.

The application is notified that the endpoint’s FIFO has been released by the USB device when TXCOMP in the 
endpoint’s UDP_CSRx register has been set. Then an interrupt for the corresponding endpoint is pending while 
TXCOMP is set.

5.

The microcontroller writes the second packet of data to be sent in the endpoint’s FIFO, writing zero or more byte 
values in the endpoint’s UDP_FDRx register,

6.

The microcontroller notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s 
UDP_CSRx register.

7.

The application clears the TXCOMP in the endpoint’s UDP_CSRx.

After the last packet has been sent, the application must clear TXCOMP once this has been set. 

TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is
pending while TXCOMP is set. 

Warning: TX_COMP must be cleared after TX_PKTRDY has been set.

Note:

Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the Data IN proto-
col layer.

The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. This also allows handling the
maximum bandwidth defined in the USB specification during bulk transfer. To be able to guarantee a constant or the
maximum bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being
sent by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other
one is locked by the USB device.

USB Bus Packets

Data IN 2

Data IN

NAK

ACK

Data IN 1

FIFO (DPR)
Content

Data IN 2

Load In Progress

Data IN 1

Cleared by Firmware

DPR access by the firmware

Payload in FIFO

TXCOMP Flag
(UDP_CSRx) 

TXPKTRDY Flag
(UDP_CSRx)

PID

Data IN

Data IN

PID

PID

PID

PID

ACK

PID

Prevous Data IN TX

Microcontroller Load Data in FIFO

Data is Sent on USB Bus

Interrupt

Pending

Interrupt Pending

Set by the firmware

Set by the firmware

Cleared by

Firmware

Cleared by Hw

Cleared by Hw

DPR access by the hardware