Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Scheda Tecnica
Codici prodotto
AT91SAM9N12-EK
550
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
33.7.11 UDP Endpoint Control and Status Register (Isochronous Endpoints)
Name:
UDP_CSRx [x = 0..5] (ISOENDPT)
Address:
0xF803C030
Access:
Read-write
• TXCOMP: Generates an IN Packet with Data Previously Written in the DPR
This flag generates an interrupt while it is set to one.
Write (Cleared by the firmware):
0 = Clear the flag, clear the interrupt.
1 = No effect.
Read (Set by the USB peripheral):
0 = Data IN transaction has not been acknowledged by the Host.
1 = Data IN transaction is achieved, acknowledged by the Host.
After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the host has
acknowledged the transaction.
acknowledged the transaction.
• RX_DATA_BK0: Receive Data Bank 0
This flag generates an interrupt while it is set to one.
Write (Cleared by the firmware):
0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0.
1 = To leave the read value unchanged.
Read (Set by the USB peripheral):
0 = No data packet has been received in the FIFO's Bank 0.
1 = A data packet has been received, it has been stored in the FIFO's Bank 0.
When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the
microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through
the UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clear-
ing RX_DATA_BK0.
microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through
the UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clear-
ing RX_DATA_BK0.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing DPR.
• RXSETUP: Received Setup
This flag generates an interrupt while it is set to one.
Read:
0 = No setup packet available.
1 = A setup data packet has been sent by the host and is available in the FIFO.
31
30
29
28
27
26
25
24
–
–
–
–
–
RXBYTECNT
23
22
21
20
19
18
17
16
RXBYTECNT
15
14
13
12
11
10
9
8
EPEDS
–
–
–
DTGLE
EPTYPE
7
6
5
4
3
2
1
0
DIR
RX_DATA_BK1 FORCESTALL
TXPKTRDY
ISOERROR
RXSETUP
RX_DATA_ BK0
TXCOMP