Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Scheda Tecnica
Codici prodotto
AT91SAM9X25-EK
197
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
22.13.10PMC Clock Generator PLLA Register
Name:
CKGR_PLLAR
Address:
0xFFFFFC28
Access:
Read-write
Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC.
Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
• DIVA: Divider A
• PLLACOUNT: PLLA Counter
Specifies the number of slow clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• OUTA: PLLA Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Characteris-
tics section of the product datasheet.
tics section of the product datasheet.
• MULA: PLLA Multiplier
0 = The PLLA is deactivated.
1 up to 254 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA+ 1.
31
30
29
28
27
26
25
24
–
–
1
–
–
MULA
23
22
21
20
19
18
17
16
MULA
15
14
13
12
11
10
9
8
OUTA
PLLACOUNT
7
6
5
4
3
2
1
0
DIVA
Value
Divider Selected
0
Divider output is 0
1
Divider is bypassed
2 - 255
Divider output is the selected clock divided by DIVA.