Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Scheda Tecnica
Codici prodotto
AT91SAM9X25-EK
447
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
Figure 30-20.Self Refresh and Automatic Update
Figure 30-21.Automatic Update During AUTO-REFRESH Command and SDRAM Access
30.5.4.2 Power-down Mode
This mode is activated by setting the low-power command bits [LPCB] to ‘10’.
Power-down mode is used when no access to the SDRAM device is possible. In this mode, power consumption is
greater than in self refresh mode. This state is similar to normal mode (No low-power mode/No self refresh mode), but
the CKE pin is low and the input and output buffers are deactivated as soon the SDRAM device is no longer accessible.
In contrast to self refresh mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64
ms). As no auto-refresh operations are performed in this mode, the DDRSDRC carries out the refresh operation. In order
to exit low-power mode, a NOP command is required in the case of Low-power SDR-SDRAM and SDR-SDRAM devices.
In the case of Low-power DDR1-SDRAM devices, the controller generates a NOP command during a delay of at least
TXP. In addition, Low-power DDR1-SDRAM and DDR2-SDRAM must remain in power-down mode for a minimum period
of TCKE periods.
greater than in self refresh mode. This state is similar to normal mode (No low-power mode/No self refresh mode), but
the CKE pin is low and the input and output buffers are deactivated as soon the SDRAM device is no longer accessible.
In contrast to self refresh mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64
ms). As no auto-refresh operations are performed in this mode, the DDRSDRC carries out the refresh operation. In order
to exit low-power mode, a NOP command is required in the case of Low-power SDR-SDRAM and SDR-SDRAM devices.
In the case of Low-power DDR1-SDRAM devices, the controller generates a NOP command during a delay of at least
TXP. In addition, Low-power DDR1-SDRAM and DDR2-SDRAM must remain in power-down mode for a minimum period
of TCKE periods.
The exit procedure is faster than in self refresh mode. See
. The DDRSDRC returns to power-
down mode as soon as the SDRAM device is not selected. It is possible to define when power-down mode is enabled by
setting the register LPR, timeout command bit.
setting the register LPR, timeout command bit.
NOP
NOP
PRCHG
MRS
ARFSH
NOP
0
Tmrd
Enter Self Refresh
Mode
Mode
SDCLK
A[12:0]
COMMAND
CKE
BA[1:0]
2
NOP
Update Extended Mode
register
register
Trp
Pasr-Tcr-Ds
NOP
NOP
PRCHALL
MRS
ARFSH
NOP
0
Trfc
SDCLK
A[12:0]
COMMAND
CKE
BA[1:0]
2
NOP
Update Extended mode
register
register
Trp
Pasr-Tcr-Ds
ACT
0
Tmrd