Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Scheda Tecnica
Codici prodotto
AT91SAM9X25-EK
811
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no
key is pressed on a keyboard.
key is pressed on a keyboard.
If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the
start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of
the end of frame when the idle state on RXD is detected.
start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of
the end of frame when the idle state on RXD is detected.
If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a
periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard.
periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard.
shows the block diagram of the Receiver Time-out feature.
Figure 39-24.Receiver Time-out Block Diagram
gives the maximum time-out period for some standard baud rates.
39.7.3.12 Framing Error
The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is
detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized.
detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized.
A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in
the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR)
with the RSTSTA bit to 1.
the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR)
with the RSTSTA bit to 1.
Table 39-11. Maximum Time-out Period
Baud Rate
Bit Time
Time-out
bit/sec
µs
ms
600
1 667
109 225
1 200
833
54 613
2 400
417
27 306
4 800
208
13 653
9 600
104
6 827
14400
69
4 551
19200
52
3 413
28800
35
2 276
33400
30
1 962
56000
18
1 170
57600
17
1 138
200000
5
328
16-bit Time-out
Counter
0
TO
TIMEOUT
Baud Rate
Clock
=
Character
Received
RETTO
Load
Clock
16-bit
Value
STTTO
D
Q
1
Clear