Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Scheda Tecnica

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SAM9G25 [DATASHEET]

11032D–ATARM–10-Mar-2014

In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS3) always have the same 
timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write 
lines (NWR0 to NWR3) in byte write access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the 
same way, NCS represents one of the NCS[0..5] chip select lines.

The read cycle is shown on 

.

The read cycle starts with the address setting on the memory address bus, i.e.: 

{A[25:2], A1, A0} for 8-bit devices

{A[25:2], A1} for 16-bit devices

A[25:2] for 32-bit devices.

The NRD signal is characterized by a setup timing, a pulse width and a hold timing.

1.

NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge;

2.

NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge;

3.

NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge.

Similarly, the NCS signal can be divided into a setup time, pulse length and hold time:

1.

NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 

2.

NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge;

3.

NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge.

A[25:2]

NBS0,NBS1,
NBS2,NBS3,
A0, A1

NCS

NRD_SETUP

NRD_PULSE

NRD_HOLD

MCK

NRD

D[31:0]

NCS_RD_SETUP

NCS_RD_PULSE

NCS_RD_HOLD

NRD_CYCLE