Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Scheda Tecnica

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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

Usually, a microcontroller system has only a single processor and no caches. In such a system, program the MPU as
follows:

In most microcontroller implementations, the shareability and cache policy attributes do not affect the system behavior.
However, using these settings for the MPU regions can make the application code more portable. The values given are
for typical situations. In special systems, such as multiprocessor designs or designs with a separate DMA engine, the
shareability attribute might be important. In these cases, refer to the recommendations of the memory device
manufacturer.

Flash memory

b000

1

0

0

Normal memory, non-shareable, write-through

Internal SRAM

b000

1

0

1

Normal memory, shareable, write-through

External SRAM

b000

1

1

1

Normal memory, shareable, write-back, write-allocate

Peripherals

b000

0

1

1

Device memory, shareable