Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Scheda Tecnica
Codici prodotto
ATSAM4S-XPLD
564
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 31-6. Transmitter Clock Management
31.7.1.3 Receiver Clock Management
The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O
pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can
be inverted independently by the CKI bits in SSC_RCMR.
pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can
be inverted independently by the CKI bits in SSC_RCMR.
The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is
configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs.
Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO
field) can lead to unpredictable results.
configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs.
Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO
field) can lead to unpredictable results.
Figure 31-7. Receiver Clock Management
31.7.1.4 Serial Clock Ratio Considerations
The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK
pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on
the RK pin is:
pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on
the RK pin is:
Master Clock divided by 2 if Receiver Frame Synchro is input
Master Clock divided by 3 if Receiver Frame Synchro is output
TK (pin)
Receiver
Clock
Divider
Clock
CKS
CKO
Data Transfer
CKI
CKG
Transmitter
Clock
Clock
Clock
Output
Output
MUX
Tri_state
Controller
Tri-state
Controller
INV
MUX
RK (pin)
Transmitter
Clock
Divider
Clock
CKS
CKO
Data Transfer
CKI
CKG
Receiver
Clock
Clock
Clock
Output
Output
MUX
Tri-state
Controller
Tri-state
Controller
INV
MUX