Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Scheda Tecnica

 860

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

Note:

1.

See 

When center aligned, the channel counter increases up to CPRD and decreases down to 0. This ends the period.

When left aligned, the channel counter increases up to CPRD and is reset. This ends the period. 

Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned channel.

Waveforms are fixed at 0 when:



CDTY = CPRD and CPOL = 0



CDTY = 0 and CPOL = 1

Waveforms are fixed at 1 (once the channel is enabled) when:



CDTY = 0 and CPOL = 0



CDTY = CPRD and CPOL = 1

The waveform polarity must be set before enabling the channel. This immediately affects the channel output level. 

Modifying CPOL in 

behavior of the device being driven by PWM.

Besides generating output signals OCx, the comparator generates interrupts in function of the counter value. When the
output waveform is left aligned, the interrupt occurs at the end of the counter period. When the output waveform is center
aligned, the bit CES of the PWM_CMRx register defines when the channel counter interrupt occurs. If CES is set to 0, the
interrupt occurs at the end of the counter period. If CES is set to 1, the interrupt occurs at the end of the counter period
and at half of the counter period. 

 illustrates the counter interrupts in function of the configuration.

OC0

OC1

Period

No overlap