Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Scheda Tecnica

 957

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

/// Clears the specified bit(s) in the UDP_CSR register.

/// \param endpoint The endpoint number of the CSR to process.

/// \param flags The bitmap to clear to 0.

#define CLEAR_CSR(endpoint, flags) \

{ \

volatile unsigned int reg; \

reg = AT91C_BASE_UDP->UDP_CSR[endpoint]; \

reg |= REG_NO_EFFECT_1_ALL; \

reg &= ~(flags); \

AT91C_BASE_UDP->UDP_CSR[endpoint] = reg; \

for( nop_count=0; nop_count<15; nop_count++ ) {\

nop();\

}\

}

In a preemptive environment, set or clear the flag and wait for a time of 1 UDPCK clock cycle and

1peripheral clock cycle. However, RX_DATA_BK0, TXPKTRDY, RX_DATA_BK1 require wait times of 3 UDPCK

clock cycles and 5 peripheral clock cycles before accessing DPR.

This flag generates an interrupt while it is set to one.

Write (Cleared by the firmware):

0 = Clear the flag, clear the interrupt.

1 = No effect.

Read (Set by the USB peripheral):

0 = Data IN transaction has not been acknowledged by the Host.

1 = Data IN transaction is achieved, acknowledged by the Host.

After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the host has 
acknowledged the transaction.

This flag generates an interrupt while it is set to one.

Write (Cleared by the firmware):

0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0.

1 = To leave the read value unchanged.

Read (Set by the USB peripheral):

0 = No data packet has been received in the FIFO's Bank 0.

1 = A data packet has been received, it has been stored in the FIFO's Bank 0.

When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the 
microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through 
the UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clear-
ing RX_DATA_BK0. 

After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing 
DPR.