Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Scheda Tecnica

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Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

The RTC counter supports three RTC operating modes: 32-bit Counter, 16-bit Counter and Clock/Calendar. The 
operating mode is selected by the Operating Mode bit group in the Control register (CTRL.MODE). 

When the RTC Operating Mode bits in the Control register (CTRL.MODE) are zero, the counter operates in 32-bit 
Counter mode. The block diagram of this mode is shown in 

. When the RTC is enabled, the counter will 

increment on every 0-to-1 transition of CLK_RTC_CNT. The counter will increment until it reaches the top value of 
0xFFFFFFFF, and then wrap to 0x00000000. This sets the Overflow Interrupt flag in the Interrupt Flag Status and Clear 
register (INTFLAG.OVF). 

The RTC counter value can be read from or written to the Counter Value register (COUNT) in 32-bit format. 

The counter value is continuously compared with the 32-bit Compare register (COMP0). When a compare match occurs, 
the Compare 0Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMP0) is set on the next 0-to-1 
transition of CLK_RTC_CNT. 

If the Clear on Match bit in the Control register (CTRL.MATCHCLR) is one, the counter is cleared on the next counter 
cycle when a compare match with COMP0 occurs. This allows the RTC to generate periodic interrupts or events with 
longer periods than are possible with the prescaler events. Note that when CTRL.MATCHCLR is one, INTFLAG.CMP0 
and INTFLAG.OVF will both be set simultaneously on a compare match with COMP0. 

When CTRL.MODE is one, the counter operates in 16-bit Counter mode as shown in 

. When the RTC is 

enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. In 16-bit Counter mode, the 16-bit 
Period register (PER) holds the maximum value of the counter. The counter will increment until it reaches the PER value, 
and then wrap to 0x0000. This sets the Overflow Interrupt flag in the Interrupt Flag Status and Clear register 
(INTFLAG.OVF). 

The RTC counter value can be read from or written to the Counter Value register (COUNT) in 16-bit format. 

The counter value is continuously compared with the 16-bit Compare registers (COMPn, n=0–1). When a compare 
match occurs, the Compare n Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn, n=0–1) is set 
on the next 0-to-1 transition of CLK_RTC_CNT.

When CTRL.MODE is two, the counter operates in Clock/Calendar mode, as shown in 

enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The selected clock source and RTC 
prescaler must be configured to provide a 1Hz clock to the counter for correct operation in this mode. 

The time and date can be read from or written to the Clock Value register (CLOCK) in a 32-bit time/date format. Time is 
represented as:

z

Seconds 

z

Minutes 

z

Hours

Hours can be represented in either 12- or 24-hour format, selected by the Clock Representation bit in the Control register 
(CTRL.CLKREP). This bit can be changed only while the RTC is disabled. 

Date is represented as:

z

Day as the numeric day of the month (starting at 1) 

z

Month as the numeric month of the year (1 = January, 2 = February, etc.)

z

Year as a value counting the offset from a reference value that must be defined in software

The date is automatically adjusted for leap years, assuming every year divisible by 4 is a leap year. Therefore, the 
reference value must be a leap year, e.g. 2000. The RTC will increment until it reaches the top value of 23:59:59 
December 31 of year 63, and then wrap to 00:00:00 January 1 of year 0. This will set the Overflow Interrupt flag in the 
Interrupt Flag Status and Clear registers (INTFLAG.OVF).