Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Scheda Tecnica

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ATSAMD20-XPRO
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Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
9.
Memories
9.1
Embedded Memories
z
Internal high-speed flash
z
Internal high-speed RAM, single-cycle access at full speed
z
Dedicated flash area for EEPROM emulation
9.2
Physical Memory Map
The High-Speed bus is implemented as a Bus Matrix. Refer to 
 for details. All High-
Speed bus addresses are fixed, and they are never remapped. The 32-bit physical address space is mapped as follows:
Table 9-1.
SAM D20 Physical Memory Map
Note:
1.
x = G, J or E. Refer to 
 for details. 
Table 9-2.
Flash Memory Parameters
Notes: 1.
x = G, J or E. Refer to 
 for details.
2.
The number of pages (NVMP) and page size (PSZ) can be read from the NVM Pages and Page Size bits in the NVM Parameter register in the 
NVMCTRL (PARAM.NVMP and PARAM.PSZ, respectively). Refer to 
 for details. 
Memory
Start address
Size
SAMD20x18
SAMD20x17
SAMD20x16
SAMD20x15
SAMD20x14
Embedded Flash
0x00000000
256KB
128KB
64KB
32KB
16KB
Embedded SRAM
0x20000000
32KB
16KB
8KB
4KB
2KB
AHB-APB Bridge A
0x40000000
64KB
64KB
64KB
64KB
64KB
AHB-APB Bridge B
0x41000000
64KB
64KB
64KB
64KB
64KB
AHB-APB Bridge C
0x42000000
64KB
64KB
64KB
64KB
64KB
Device
Flash Size 
Number of Pages (NVMP)
Page Size (PSZ)
Row Size
ATSAMD20x18
256KB
4096
64 bytes
4 pages = 256 bytes
ATSAMD20x17
128KB
2048
64 bytes
4 pages = 256 bytes
ATSAMD20x16
64KB
1024
64 bytes
4 pages = 256 bytes
ATSAMD20x15
32KB
512
64 bytes
4 pages = 256 bytes
ATSAMD20x14
16KB
256
64 bytes
4 pages = 256 bytes