Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Scheda Tecnica

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Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

To issue a command, the CTRLA.CMD bits must be written along with the CTRLA.CMDEX value. When a command is 
issued, INTFLAG.READY will be cleared until the command has completed. Any commands written while 
INTFLAG.READY is low will be ignored. Read the 

 register description for more details.

The CTRLB register must be used to control the power reduction mode, read wait states and the write mode.

Reading from the NVM main address space is performed via the AHB bus by addressing the NVM main address space 
or auxiliary address space directly. Read data is available after the configured number of read wait states (CTRLB.RWS) 
set in the NVM Controller, has passed.

The number of cycles data are delayed to the AHB bus is determined by the read wait states. Examples of using zero 
and one wait states are shown in 

The NVM Controller requires that an erase must be done before programming. The entire NVM main address space can 
be erased by a debugger Chip Erase command. Alternatively, rows can be individually erased by the Erase Row 
command.

After programming, the region that the page resides in can be locked to prevent spurious write or erase sequences. 
Locking is performed on a per-region basis, and so locking a region locks all pages inside the region.

Data to be written to the NVM block are first written and stored in an internal buffer called the page buffer. The page 
buffer contains the same number of bytes as an NVM page. Writes to the page buffer must be 16 or 32 bits. 8-bit writes 
to the page buffer is not allowed, and will cause a system exception.

Writing to the NVM block via the AHB bus is performed by a load operation to the page buffer. For each AHB bus write, 
the address is stored in the ADDR register. After the page buffer has been loaded with the required number of bytes, the 
page can be written to the addressed location by setting CMD to Write Page and setting the key value to CMDEX. The 
LOAD bit in the STATUS register indicates whether the page buffer has been loaded or not. Before writing the page to 
memory, the accessed row must be erased.

By default, automatic page writes are enabled (MANW=0). This will trigger a write operation to the page addressed by 
ADDR when the last location of the page is written.

Because the address is automatically stored in ADDR during the I/O bus write operation, the last given address will be 
present in the ADDR register. There is no need to load the ADDR register manually, unless a different page in memory is 
to be written.

 

Rd 0

Rd 1

Idle

Data 0

Data 1

Rd 0

Rd 1

Idle

Data 0

Data 1

AHB Command

AHB Slave Ready

AHB Slave Data

AHB Command

AHB Slave Ready

AHB Slave Data