Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Scheda Tecnica
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ATSAMD20-XPRO
305
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
21.8.13 Pin Configuration y
There are up to 32 Pin Configuration registers in each group, one for each I/O line. The y denotes the number of the I/O
line, while the x denotes the number of the group.
line, while the x denotes the number of the group.
Name:
PINCFGy
Offset:
0x40+y*0x1+x*0x80 [n=0..31] (x=0..1)
Reset:
0x00
Property:
Write-Protected
z
Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 6 – DRVSTR: Output Driver Strength Selection
This bit controls the output driver strength of an I/O pin configured as an output.
This bit controls the output driver strength of an I/O pin configured as an output.
0: Pin drive strength is set to normal drive strength.
1: Pin drive strength is set to stronger drive strength.
z
Bits 5:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – PULLEN: Pull Enable
This bit enables the internal pull-up or pull-down resistor of an I/O pin configured as an input.
This bit enables the internal pull-up or pull-down resistor of an I/O pin configured as an input.
0: Internal pull resistor is disabled, and the input is in a high-impedance configuration.
1: Internal pull resistor is enabled, and the input is driven to a defined logic level in the absence of external input.
z
Bit 1 – INEN: Input Enable
This bit controls the input buffer of an I/O pin configured as either an input or output.
This bit controls the input buffer of an I/O pin configured as either an input or output.
0: Input buffer for the I/O pin is disabled, and the input value will not be sampled.
1: Input buffer for the I/O pin is enabled, and the input value will be sampled when required.
Writing a zero to this bit disables the input buffer completely, preventing read-back of the physical pin state when
the pin is configured as either an input or output.
the pin is configured as either an input or output.
z
Bit 0 – PMUXEN: Peripheral Multiplexer Enable
This bit enables or disables the peripheral multiplexer selection set in the Peripheral Multiplexing register (PMUXn)
to enable or disable alternative peripheral control over an I/O pin direction and output drive value.
This bit enables or disables the peripheral multiplexer selection set in the Peripheral Multiplexing register (PMUXn)
to enable or disable alternative peripheral control over an I/O pin direction and output drive value.
0: The peripheral multiplexer selection is disabled, and the PORT registers control the direction and output drive
value.
value.
1: The peripheral multiplexer selection is enabled, and the selected peripheral controls the direction and output
drive value.
drive value.
Writing a zero to this bit allows the PORT to control the pad direction via the Data Direction register (DIR) and out-
put drive value via the Data Output Value register (OUT). The peripheral multiplexer value in PMUXn is ignored.
put drive value via the Data Output Value register (OUT). The peripheral multiplexer value in PMUXn is ignored.
Writing a one to this bit enables the peripheral selection in PMUXn to control the pad. In this configuration, the
physical pin state may still be read from the Data Input Value register (IN) if PINCFGy.INEN is set.
physical pin state may still be read from the Data Input Value register (IN) if PINCFGy.INEN is set.
Bit
7
6
5
4
3
2
1
0
DRVSTR
PULLEN
INEN
PMUXEN
Access
R
R/W
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0