Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Scheda Tecnica
Codici prodotto
ATSAMD20-XPRO
383
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
25.8.7 Interrupt Flag Status and Clear
Name:
INTFLAG
Offset:
0x0E
Reset:
0x00
Property:
-
z
Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – RXC: Receive Complete
This flag is cleared by reading the Data (DATA) register or by disabling the receiver.
This flag is cleared by reading the Data (DATA) register or by disabling the receiver.
This flag is set when there are unread data in the receive buffer. If address matching is enabled, the first data
received in a transaction will be an address.
received in a transaction will be an address.
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
z
Bit 1 – TXC: Transmit Complete
This flag is cleared by writing a one to it or by writing new data to DATA.
This flag is cleared by writing a one to it or by writing new data to DATA.
In master mode, this flag is set when the data have been shifted out and there are no new data in DATA.
In slave mode, this flag is set when the _SS pin is pulled high. If address matching is enabled, this flag is only set
if the transaction was initiated with an address match.
if the transaction was initiated with an address match.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the flag.
z
Bit 0 – DRE: Data Register Empty
This flag is cleared by writing new data to DATA.
This flag is cleared by writing new data to DATA.
This flag is set when DATA is empty and ready for new data to transmit.
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
Bit
7
6
5
4
3
2
1
0
RXC
TXC
DRE
Access
R
R
R
R
R
R
R/W
R
Reset
0
0
0
0
0
0
0
0