Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Scheda Tecnica
Codici prodotto
ATSAMD20-XPRO
400
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
26.6.6 Synchronization
Due to the asynchronicity between CLK_SERCOMx_APB and GCLK_SERCOMx_CORE, some registers must be
synchronized when accessed. A register can require:
synchronized when accessed. A register can require:
z
Synchronization when written
z
Synchronization when read
z
Synchronization when written and read
z
No synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following register needs synchronization when written:
z
Data (DATA) when in smart mode
The following bits need synchronization when written:
z
Software Reset bit in the Control A register (CTRLA.SWRST)
z
Enable bit in the Control A register (CTRLA.ENABLE)
z
Write to Bus State bits in the Status register (STATUS.BUSSTATE)
z
Address bits in the Address register (ADDR.ADDR) when in master operation
Write-synchronization is denoted by the Write-Synchronized property in the register description.
The following register needs synchronization when read:
z
Data (DATA) when in smart mode
Read-synchronization is denoted by the Read-Synchronized property in the register description.