Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Scheda Tecnica
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ATSAMD20-XPRO
476
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
28.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
28.5.1 I/O Lines
Using the ADC's I/O lines requires the I/O pins to be configured using the port configuration (PORT).
for details.
28.5.2 Power Management
The ADC will continue to operate in any sleep mode where the selected source clock is running. The ADC’s interrupts
can be used to wake up the device from sleep modes. The events can trigger other operations in the system without
exiting the sleep modes. Refer to
can be used to wake up the device from sleep modes. The events can trigger other operations in the system without
exiting the sleep modes. Refer to
for details on the different sleep modes.
28.5.3 Clocks
The ADC bus clock (CLK_ADC_APB) can be enabled and disabled in the Power Manager, and the default state of
CLK_ADC_APB can be found in the
CLK_ADC_APB can be found in the
A generic clock (GCLK_ADC) is required to clock the ADC. This clock must be configured and enabled in the Generic
Clock Controller (GCLK) before using the ADC. Refer
Clock Controller (GCLK) before using the ADC. Refer
This generic clock is asynchronous to the bus clock (CLK_ADC_APB). Due to this asynchronicity, writes to certain
registers will require synchronization between the clock domains. Refer to
registers will require synchronization between the clock domains. Refer to
details.
28.5.4 DMA
Not applicable.
28.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using ADC interrupts requires the interrupt controller to
be configured first. Refer to
be configured first. Refer to
28.5.6 Events
Events are connected to the Event System. Refer to
for details.
28.5.7 Debug Operation
When the CPU is halted in debug mode, the ADC will halt normal operation. The ADC can be forced to continue
operation during debugging. Refer to the Debug Control register (
operation during debugging. Refer to the Debug Control register (
) for details.
28.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following register:
following register:
z
Interrupt Flag Status and Clear register (
)
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode or the CPU reset is extended, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to
Write-protection does not apply for accesses through an external debugger. Refer to
28.5.9 Analog Connections
I/O-pins AIN0 to AIN19 as well as the AREFA/AREFB reference voltage pin are analog inputs to the ADC.