Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Scheda Tecnica
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ATSAMD20-XPRO
94
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
14.8.4 Generic Clock Generator Control
This register allows the user to configure one of the generic clock generators, as specified in the GENCTRL.ID bit group.
To write to the GENCTRL register, do a 32-bit write with all configurations and the ID.
To write to the GENCTRL register, do a 32-bit write with all configurations and the ID.
To read the GENCTRL register, first do an 8-bit write to the GENCTRL.ID bit group with the ID of the generic clock
generator those configuration is to be read, and then read the GENCTRL register.
generator those configuration is to be read, and then read the GENCTRL register.
Name:
GENCTRL
Offset:
0x4
Reset:
0x00010600
Property:
Write-protected, Write-Synchronized
Note:
1.
for reset value of other generators.
z
Bits 31:22 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 21 – RUNSTDBY: Run in Standby
This bit is used to keep the generic clock generator running when it is configured to be output to its dedicated
GCLK_IO pin. If GENCTRL.OE is zero, this bit has no effect and the generic clock generator will only be running if
a peripheral requires the clock.
This bit is used to keep the generic clock generator running when it is configured to be output to its dedicated
GCLK_IO pin. If GENCTRL.OE is zero, this bit has no effect and the generic clock generator will only be running if
a peripheral requires the clock.
0: The generic clock generator is stopped in standby and the GCLK_IO pin state (one or zero) will be dependent
on the setting in GENCTRL.OOV.
on the setting in GENCTRL.OOV.
1: The generic clock generator is kept running and output to its dedicated GCLK_IO pin during standby mode.
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
RUNSTDBY
DIVSEL
OE
OOV
IDC
GENEN
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
SRC[4:0]
Access
R
R
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ID[3:0]
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0