Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK ATSAM4E-EK Scheda Tecnica

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

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The DACC uses the peripheral clock divided by either two or four to perform conversions. 

This clock is named

DAC clock. 

If the peripheral clock frequency is above 100 MHz, the CLKDIV bit must be set in the DACC Mode

Register (DACC_MR). Once a conversion starts, the DACC takes 

25 clock periods to provide the analog result on

the selected analog output.

When a conversion is completed, the resulting analog value is available at the selected DACC channel output and
the EOC bit in the 

 (DACC_ISR) is set.

Reading the DACC_ISR clears the EOC bit.

In free-running mode, conversion starts as soon as at least one channel is enabled and data is written in the 

 (DACC_CDR). 

25

 DAC clock periods later, the converted data is available at the

corresponding analog output as stated above.

In external trigger mode, the conversion waits for a rising edge on the selected trigger to begin.

Warning: Disabling the external trigger mode automatically sets the DACC in free-running mode.

A four half-word FIFO is used to handle the data to be converted.

If the TXRDY flag in the DACC_ISR is active, the DACC is ready to accept conversion requests by writing data into
the DATA field in the DACC_CDR. Data which cannot be converted immediately is stored in the DACC FIFO.

When the FIFO is full or when the DACC is not ready to accept conversion requests, the TXRDY flag is inactive.

The WORD field of the 

 (DACC_MR) allows the user to switch between half-word and word

transfers in order to write into the FIFO.

In half-word transfer mode, only the 16 LSBs of DACC_CDR data are processed. Bits DATA[15:0] are stored in the
FIFO. Bits DATA[11:0] are used as data. Bits DATA[15:12] are used for channel selection if the TAG field is set in
DACC_MR.

In word transfer mode, each time DACC_CDR is written, two data items are stored in the FIFO. The first data item
sampled for conversion is DATA[15:0] and the second is DATA[31:16]. Bits DATA[15:12] and DATA[31:28] are
used for channel selection if the TAG field is set in DACC_MR.

Warning: Writing in the DACC_CDR while the TXRDY flag is inactive will corrupt FIFO data.

There are two ways to select the channel to perform data conversion.



By default, the USER_SEL field of the DACC_MR is used. Data requests are converted to the channel 
selected with the USER_SEL field.



Alternatively, the tag mode can be used by setting the TAG field of the DACC_MR to 1. In this mode, the two 
bits, DACC_CDR[13:12], which are otherwise unused, are employed to select the channel in the same way 
as with the USER_SEL field. Finally, if the WORD field is set, the two bits, DACC_CDR[13:12] are used for 
channel selection of the first data and the two bits, DACC_CDR[29:28] for channel selection of the second 
data.