Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK ATSAM4E-EK Scheda Tecnica
Codici prodotto
ATSAM4E-EK
965
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
Figure 39-5.
Example of Transfer with PDC
39.6.10 Trigger Conditions
In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined.
The ABETRG bit in the TC_CMR selects TIOA or TIOB input signal as an external trigger or the trigger signal from
the output comparator of the PWM module. The External Trigger Edge Selection parameter (ETRGEDG field in
TC_CMR) defines the edge (rising, falling, or both) detected to generate an external trigger. If ETRGEDG = 0
(none), the external trigger is disabled.
the output comparator of the PWM module. The External Trigger Edge Selection parameter (ETRGEDG field in
TC_CMR) defines the edge (rising, falling, or both) detected to generate an external trigger. If ETRGEDG = 0
(none), the external trigger is disabled.
TIOB
TIOA
RA
RB
Transfer to System Memory
Peripheral trigger
RA
RB
RA
RB
T1,T2,T3,T4 = System Bus load dependent (t
min
= 8 peripheral clocks)
T1
T2
T3
T4
ETRGEDG = 1, LDRA = 1, LDRB = 2, ABETRG = 0,
ETRGEDG = 3, LDRA = 3, LDRB = 0, ABETRG = 0
TIOB
TIOA
RA
Transfer to System Memory
Peripheral trigger
RA
RA
T1,T2,T3,T4 = System Bus load dependent (t
min
= 8 peripheral clocks)
T1
T2
T3
T4
RA
RA