Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Scheda Tecnica
Codici prodotto
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
198
The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Registers.
shows how the interrupts, or IRQ numbers, map onto the interrupt registers and corresponding CMSIS variables
that have one bit per interrupt.
Note:
1. Each array element corresponds to a single NVIC register, for example the ICER[0] element corresponds to the
ICER0.
Table 12-30.
Mapping of Interrupts to the Interrupt Variables
Interrupts
CMSIS Array Elements
Set-enable
Clear-enable
Set-pending
Clear-pending
Active Bit
0–31
ISER[0]
ICER[0]
ISPR[0]
ICPR[0]
IABR[0]
32–35
ISER[1]
ICER[1]
ISPR[1]
ICPR[1]
IABR[1]