Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Scheda Tecnica

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

1. Select the manual write of duty-cycle values and the manual update by setting the UPDM field to ‘0’ in the 

PWM_SCM register

2. Define the synchronous channels by the SYNCx bits in the PWM_SCM register.
3. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
4. If an update of the period value and/or the duty-cycle values and/or the dead-time values is required, write 

registers that need to be updated (PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPDx).

5. Set UPDULOCK to ‘1’ in PWM_SCUC.
6. The update of the registers will occur at the beginning of the next PWM period. At this moment the 

UPDULOCK bit is reset, go to 

) for new values.

In this mode, the update of the period value, the duty-cycle values, the dead-time values and the update period 

value must be done by writing in their respective update registers with the CPU (respectively PWM_CPRDUPDx, 

PWM_CDTYUPDx, PWM_DTUPDx and PWM_SCUPUPD).
To trigger the update of the period value and the dead-time values, the user must use the bit UPDULOCK in the 

PWM_SCUC register, which allows to update synchronously (at the same PWM period) the synchronous 

channels:



If the bit UPDULOCK is set to ‘1’, the update is done at the next PWM period of the synchronous channels.



If the UPDULOCK bit is not set to ‘1’, the update is locked and cannot be performed.

After writing the UPDULOCK bit to ‘1’, it is held at this value until the update occurs, then it is read 0.
The update of the duty-cycle values and the update period is triggered automatically after an update period.
To configure the automatic update, the user must define a value for the Update Period by the UPR field in the 

PWM_SCUP register. The PWM controller waits UPR+1 period of synchronous channels before updating 

automatically the duty values and the update period value.
The status of the duty-cycle value write is reported in the 

 (PWM_ISR2) by the 

following flags:



WRDY: this flag is set to ‘1’ when the PWM Controller is ready to receive new duty-cycle values and a new 

update period value. It is reset to ‘0’ when the PWM_ISR2 register is read.

Depending on the interrupt mask in the 

 (PWM_IMR2), an interrupt can be 

generated by these flags.
Sequence for Method 2:

CCNT0

CDTYUPD

0x20

0x40

0x60

UPDULOCK

CDTY

0x20

0x40

0x60