Mikroelektronika MikroE Development Kits MIKROE-1208 Scheda Tecnica

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MIKROE-1208
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 2009-2012 Microchip Technology Inc.
DS70593D-page 191
dsPIC33FJXXXGPX06A/X08A/X10A
bit 5
ACKDT:
 Acknowledge Data bit (when operating as I
2
C master, applicable during master receive)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1
 = Send NACK during Acknowledge
0
 = Send ACK during Acknowledge
bit 4
ACKEN:
 Acknowledge Sequence Enable bit 
(when operating as I
2
C master, applicable during master receive)
1
 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. 
Hardware clear at end of master Acknowledge sequence
0
 = Acknowledge sequence not in progress
bit 3
RCEN:
 Receive Enable bit (when operating as I
2
C master)
1
 = Enables Receive mode for I
2
C. Hardware clear at end of eighth bit of master receive data byte
0
 = Receive sequence not in progress
bit 2
PEN:
 Stop Condition Enable bit (when operating as I
2
C master)
1
 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence
0
 = Stop condition not in progress
bit 1
RSEN:
 Repeated Start Condition Enable bit (when operating as I
2
C master)
1
 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of 
master Repeated Start sequence
0
 = Repeated Start condition not in progress
bit 0
SEN:
 Start Condition Enable bit (when operating as I
2
C master)
1
 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence
0
 = Start condition not in progress
REGISTER 17-1:
I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)