Olimex Open Source Hardware Embedded ARM Linux Single board computer with i.MX233 ARM926J @454Mhz IMX233-OLINUXINO-MICRO IMX233-OLINUXINO-MICRO Manuale Utente
Codici prodotto
IMX233-OLINUXINO-MICRO
OLIMEX© 2012
OLinuXino-MICRO user's manual
— Absolute accuracy of 1.3%
Security Features
— Read-only unique ID for digital rights management algorithms
— Secure boot using 128-bit AES hardware decryption
— SHA-1 hashing hardware
— Customer-programmed (OTP) 128 bit AES key is never visible to software.
— Secure boot using 128-bit AES hardware decryption
— SHA-1 hashing hardware
— Customer-programmed (OTP) 128 bit AES key is never visible to software.
External Memory Interface (EMI)
— Provides memory-mapped (load/store) access to external memories
— Supports the following types DRAM:
— 1.8V Mobile DDR
— Standard 2.5V DDR1
— Supports the following types DRAM:
— 1.8V Mobile DDR
— Standard 2.5V DDR1
Wide Assortment of External Media Interfaces
— High-speed MMC, secure digital (SD)
— Hardware Reed-Solomon Error Correction Code (ECC) engine offers industry-leading
protection and performance for NANDs.
— Hardware BCH ECC engine allowing for up to 20-bit correction and programmable
redundant area.
— Hardware Reed-Solomon Error Correction Code (ECC) engine offers industry-leading
protection and performance for NANDs.
— Hardware BCH ECC engine allowing for up to 20-bit correction and programmable
redundant area.
Dual Peripheral Bus Bridges with 18 DMA Channels
— Multiple peripheral clock domains save power while optimizing performance.
— Direct Memory Access (DMA) with sophisticated linked DMA command architecture
saves power and off-loads the CPU.
— Direct Memory Access (DMA) with sophisticated linked DMA command architecture
saves power and off-loads the CPU.
Highly Flexible Display Controller
— 8-bit data ITU-R BT.656 D1 digital video stream output mode (PAL/NTSC), with onthe-
fly RGB to YCbCr color-space-conversion.
— Flexible input formats
fly RGB to YCbCr color-space-conversion.
— Flexible input formats
Pixel Processing Pipeline (PXP)
— Provides full path from color-space conversion, scaling, alpha-blending to rotation
without intermediate memory access
— Bi-linear scaling algorithm with cropping and letterboxing
— Alpha-blend, BITBLT, color-keying
— Memory efficient block-based rotation engine
without intermediate memory access
— Bi-linear scaling algorithm with cropping and letterboxing
— Alpha-blend, BITBLT, color-keying
— Memory efficient block-based rotation engine
Integrated TV-Out Support
— Integrated PAL/NTSC TV-encoder fully pipelined to display controller’s D1 resolution
output stream
— Integrated low-power 10-bit Video DAC (VDAC) for composite analog video output.
output stream
— Integrated low-power 10-bit Video DAC (VDAC) for composite analog video output.
Data Co-Processor (DCP)
— AES 128-bit encryption/decryption
— SHA-1 hashing
— High-speed memory copy
— SHA-1 hashing
— High-speed memory copy
Three Universal Asynchronous Receiver-Transmitters (UARTs)
— Two high-speed application UARTs operating up to 3.25 Mb/s with hardware flow
control and dual DMA.
— Debug UART operates at up to 115Kb/s using programmed I/O.
control and dual DMA.
— Debug UART operates at up to 115Kb/s using programmed I/O.
I2C Master/Slave
— DMA control of an entire EEPROM or other device read/write transaction without CPU
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