Mikroelektronika MikroE Development Kits MIKROE-997 Scheda Tecnica
Codici prodotto
MIKROE-997
© 2009 Microchip Technology Inc.
DS39775C-page 409
PIC18F87J50 FAMILY
CALLW
Subroutine Call using WREG
Syntax:
CALLW
Operands:
None
Operation:
(PC + 2)
→ TOS,
(W)
→ PCL,
(PCLATH)
→ PCH,
(PCLATU)
→ PCU
Status Affected:
None
Encoding:
0000
0000
0001
0100
Description
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOP instruction while the
new next instruction is fetched.
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOP instruction while the
new next instruction is fetched.
Unlike CALL, there is no option to
update W, STATUS or BSR.
update W, STATUS or BSR.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
WREG
Push PC to
stack
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
CALLW
Before Instruction
PC
=
address (HERE)
PCLATH =
10h
PCLATU =
00h
W
=
06h
After Instruction
PC
=
001006h
TOS
=
address (HERE + 2)
PCLATH =
10h
PCLATU = 00h
W
=
06h
MOVSF
Move Indexed to f
Syntax:
MOVSF [z
s
], f
d
Operands:
0
≤ z
s
≤ 127
0
≤ f
d
≤ 4095
Operation:
((FSR2) + z
s
)
→ f
d
Status Affected:
None
Encoding:
1st word (source)
2nd word (destin.)
1st word (source)
2nd word (destin.)
1110
1111
1111
1011
ffff
ffff
0zzz
ffff
ffff
zzzz
s
ffff
d
Description:
The contents of the source register are
moved to destination register ‘f
moved to destination register ‘f
d
’. The
actual address of the source register is
determined by adding the 7-bit literal
offset ‘z
determined by adding the 7-bit literal
offset ‘z
s
’, in the first word, to the value
of FSR2. The address of the destination
register is specified by the 12-bit literal
‘f
register is specified by the 12-bit literal
‘f
d
’ in the second word. Both addresses
can be anywhere in the 4096-byte data
space (000h to FFFh).
space (000h to FFFh).
The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h.
an Indirect Addressing register, the
value returned will be 00h.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Determine
source addr
Determine
source addr
Read
source reg
Decode
No
operation
No dummy
read
No
operation
Write
register ‘f’
(dest)
Example:
MOVSF [05h], REG2
Before Instruction
FSR2
=
80h
Contents
of 85h
=
33h
REG2
=
11h
After Instruction
FSR2
=
80h
Contents
of 85h
=
33h
REG2
=
33h