Mikroelektronika MikroE Development Kits MIKROE-1104 Scheda Tecnica

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DocID15818 Rev 11

The formula above (

) is used to determine the maximum external impedance 

allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of 
sampling periods defined in the ADC_SMPR1 register.

         a

ADC accuracy vs. negative injection current: injecting a negative current on any analog 
input pins should be avoided as this significantly reduces the accuracy of the conversion 

f

Sampling rate 
(f

ADC

 = 30 MHz)

12-bit resolution

Single ADC

-

-

2

Msps

12-bit resolution

Interleave Dual ADC 

mode

-

-

3.75

Msps

12-bit resolution

Interleave Triple ADC 

mode

-

-

6

Msps

I

VREF+

ADC V

REF

 DC current 

consumption in conversion mode 

-

300

500

µA

I

VDDA

ADC VDDA DC current 
consumption in conversion mode 

-

1.6

1.8

mA

1. On devices in WLCSP64+2 package, if IRROFF is set to V

DD

, the supply voltage can drop to 1.7 V when the device 

operates in the 0 to 70 °C temperature range using an external power supply supervisor (see 

2. It is recommended to maintain the voltage difference between V

REF+

 and V

DDA 

below 1.8 V.

3. Based on characterization, not tested in production.

4. V

REF+

 is internally connected to V

DDA

 and V

REF-

 is internally connected to V

SSA

.

5. R

ADC

 maximum value is given for V

DD

=1.8 V, and minimum value for V

DD

=3.3 V.

6. For external triggers, a delay of 1/f

PCLK2

 must be added to the latency specified in 

 

1. Better performance could be achieved in restricted V

DD

, frequency and temperature ranges.

2. Based on characterization, not tested in production.

ET

Total unadjusted error

f

PCLK2

 = 60 MHz,

f

ADC

 = 30 MHz, R

AIN

 < 10 k

Ω, 

V

DDA

 = 1.8

(3)

 to 3.6 V

3. On devices in WLCSP64+2 package, if IRROFF is set to V

DD

, the supply voltage can drop to 1.7 V when 

the device operates in the 0 to 70 °C temperature range using an external power supply supervisor (see 

).

±2

±5

LSB

EO

Offset error

±1.5

±2.5

EG

Gain error

±1.5

±3

ED

Differential linearity error

±1

±2

EL

Integral linearity error

±1.5

±3

R

AIN

k 0.5

–

(

)

f

ADC

C

ADC

2

N

2

+

(

)

ln

×

×

--------------------------------------------------------------

R

ADC

–

=