Mikroelektronika MikroE Development Kits MIKROE-18 Scheda Tecnica

© 2008 Microchip Technology Inc.

DS39646C-page 143

PORTD is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output

(i.e., put the contents of the output latch on the

selected pin).

The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD. 

All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.

In 80-pin devices, PORTD is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled,
PORTD is the low-order byte of the multiplexed
address/data bus (AD<7:0>). The TRISD bits are also
overridden.

PORTD can also be configured to function as an 8-bit
wide parallel microprocessor port by setting the
PSPMODE control bit (PSPCON<4>). In this mode,
parallel port data takes priority over other digital I/O (but
not the external memory interface). When the parallel
port is active, the input buffers are TTL. For more
information, refer to Section 11.10 “Parallel Slave
Port”.

On a Power-on Reset, these pins are
configured as digital inputs.

CLRF

PORTD

;

  Initialize PORTD by

 

; clearing output

 

; data latches

CLRF

LATD

; Alternate method

; to clear output

; data latches

MOVLW

 

0CFh

;

  Value used to 

; initialize data 

; direction

MOVWF

 

TRISD

;

  Set RD<3:0> as inputs

;

  RD<5:4> as outputs

;

  RD<7:6> as inputs