STMicroelectronics FlexSPIN: SPI configurable stepper and DC multi motor driver evaluation board EVAL6460 EVAL6460 Scheda Tecnica
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EVAL6460
Power bridges
L6460
56/139
Doc ID 17713 Rev 1
14 Power
bridges
L6460 includes four H bridge power outputs (each one made by two independent half
bridges) that are configurable in several different configurations.
bridges) that are configurable in several different configurations.
Each half bridge is protected against: over-current, over-temperature and short circuit to
ground, to supply or across the load. When an over current event occurs, all outputs are
turned off (after a filter time), and the over current bit is stored in the internal status register
that can be read through SPI.
ground, to supply or across the load. When an over current event occurs, all outputs are
turned off (after a filter time), and the over current bit is stored in the internal status register
that can be read through SPI.
Positive and negative voltage spikes, which occur when switching inductive loads, are
limited by integrated freewheeling diodes (see
limited by integrated freewheeling diodes (see
).
Figure 14.
H Bridge block diagram
During the start up procedure the bridges are in high impedance and after that they can be
enabled through SPI. When a fault condition happens, i.e. an over-temperature event, the
bridges return in their start-up condition and they need to be re-enabled from the micro
controller.
enabled through SPI. When a fault condition happens, i.e. an over-temperature event, the
bridges return in their start-up condition and they need to be re-enabled from the micro
controller.
The bridges can use PWM signals internally generated or externally provided (supplied
through the GPIO pins). Internally generated PWM signals will run at approximately
31.25kHz with a duty cycle that, through serial interface, can be programmed and
incremented in steps of 1/(512*F
through the GPIO pins). Internally generated PWM signals will run at approximately
31.25kHz with a duty cycle that, through serial interface, can be programmed and
incremented in steps of 1/(512*F
osc
). To reduce the peak current requested from supply
voltage when all bridges are switching, the four internally generated PWM signals are out-
of-phase.
of-phase.
Each half bridge will use the PWM signal selected by the respective
MtrXSelPWMSideY[1:0] (X stands for 1, 2, 3 or 4; Y stands for A or B) bits in the SPI, but if
two half bridges are configured as a full bridge, only the PWM signal chosen for side A will
be used to drive the resulting H bridge.
MtrXSelPWMSideY[1:0] (X stands for 1, 2, 3 or 4; Y stands for A or B) bits in the SPI, but if
two half bridges are configured as a full bridge, only the PWM signal chosen for side A will
be used to drive the resulting H bridge.
More in detail the PWM selection truth table will be as describe in the following tables:
#ONTROL
,OW
$RIVER
,OW
$RIVER
(IGH
$RIVER
(IGH
$RIVER
#ONTROL
(/%
PS
4&/4&
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