Intel III Xeon 900 MHz 80526KY9002M Scheda Tecnica
Codici prodotto
80526KY9002M
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
4
6.2.3
MEASUREMENTS FOR THERMAL SPECIFICATIONS............................................................57
7. MECHANICAL SPECIFICATIONS ................................................................................................................58
7.1 W
EIGHT
................................................................................................................................................................. 62
7.2 C
ARTRIDGE TO
C
ONNECTOR
M
ATING
D
ETAILS
.............................................................................................. 62
7.3 S
UBSTRATE
E
DGE
F
INGER
S
IGNAL
L
ISTING
..................................................................................................... 64
8. INTEGRATION TOOLS......................................................................................................................................74
8.1 I
N
-T
ARGET
P
ROBE
(ITP)..................................................................................................................................... 74
8.1.1 PRIMARY FUNCTION ................................................................................................................................74
8.1.2 DEBUG PORT CONNECTOR DESCRIPTION ......................................................................................74
8.1.3 KEEP OUT CONCERNS .............................................................................................................................75
8.1.4 ADDITIONAL INTEGRATION TOOL MECHANICAL KEEP OUTS ................................................75
8.1.5 DEBUG PORT SIGNAL DESCRIPTIONS ...............................................................................................76
8.1.6 DEBUG PORT SIGNAL NOTES................................................................................................................78
8.1.7 Using the TAP to Communicate to the processor...................................................................................80
8.1.2 DEBUG PORT CONNECTOR DESCRIPTION ......................................................................................74
8.1.3 KEEP OUT CONCERNS .............................................................................................................................75
8.1.4 ADDITIONAL INTEGRATION TOOL MECHANICAL KEEP OUTS ................................................75
8.1.5 DEBUG PORT SIGNAL DESCRIPTIONS ...............................................................................................76
8.1.6 DEBUG PORT SIGNAL NOTES................................................................................................................78
8.1.7 Using the TAP to Communicate to the processor...................................................................................80
8.2 L
OGIC
A
NALYZER
I
NTERCONNECT
(LAI)
AND
T
RACE
C
APTURE
T
OOL
C
ONSIDERATIONS
...................... 81
8.2.1 LAI and Trace Capture Tool System Design Considerations...............................................................81
8.2.1 LAI and Trace Capture tool Mechanical Keep Outs ..............................................................................81
8.2.1 LAI and Trace Capture tool Mechanical Keep Outs ..............................................................................81
9. BOXED PROCESSOR SPECIFICATIONS ...................................................................................................82
9.1 I
NTRODUCTION
..................................................................................................................................................... 82
9.2 M
ECHANICAL
S
PECIFICATIONS
.......................................................................................................................... 82
9.2.1 BOXED PROCESSOR HEATSINK DIMENSIONS ................................................................................84
9.2.2 BOXED PROCESSOR HEATSINK WEIGHT..........................................................................................84
9.2.3 BOXED PROCESSOR RETENTION MECHANISM ..............................................................................84
9.2.2 BOXED PROCESSOR HEATSINK WEIGHT..........................................................................................84
9.2.3 BOXED PROCESSOR RETENTION MECHANISM ..............................................................................84
9.3 T
HERMAL
S
PECIFICATIONS
................................................................................................................................. 85
9.3.1 Boxed Processor Cooling Requirements ..................................................................................................85
9.3.2 Boxed Processor Passive Heatsink Performance ...................................................................................85
9.3.2 Optional auxiliary fan attachment.............................................................................................................86
9.3.2 Boxed Processor Passive Heatsink Performance ...................................................................................85
9.3.2 Optional auxiliary fan attachment.............................................................................................................86
10. APPENDIX .............................................................................................................................................................89
10.1 A
LPHABETICAL
S
IGNALS
R
EFERENCE
............................................................................................................ 89
10.1.1 A[35:03]# (I/O) ..........................................................................................................................................89
10.1.2 A20M# (I) ....................................................................................................................................................89
10.1.3 ADS# (I/O) ...................................................................................................................................................89
10.1.4 AERR# (I/O) ................................................................................................................................................89
10.1.5 AP[1:0]# (I/O) ............................................................................................................................................89
10.1.6 BCLK (I).......................................................................................................................................................90
10.1.7 BERR# (I/O) ................................................................................................................................................90
10.1.8 BINIT# (I/O) ................................................................................................................................................90
10.1.9 BNR# (I/O)...................................................................................................................................................90
10.1.10 BP[3:2]# (I/O) ..........................................................................................................................................90
10.1.11 BPM[1:0]# (I/O) ......................................................................................................................................90
10.1.12 BPRI# (I)....................................................................................................................................................90
10.1.13 BR0# (I/O), BR[3:1]# (I) ........................................................................................................................90
10.1.14 BR0# (I/O), BR[3:1]# (I) ........................................................................................................................91
10.1.15 CORE_AN_SENSE (O) ...........................................................................................................................92
10.1.16 D[63:00]# (I/O) ........................................................................................................................................92
10.1.17 DBSY# (I/O) ..............................................................................................................................................92
10.1.18 DEFER# (I) ...............................................................................................................................................92
10.1.19 DEP[7:0]# (I/O) .......................................................................................................................................92
10.1.20 DRDY# (I/O)..............................................................................................................................................92
10.1.21 FERR# (O) .................................................................................................................................................93
10.1.22 FLUSH# (I)................................................................................................................................................93
10.1.23 HIT# (I/O), HITM# (I/O).........................................................................................................................93
10.1.24 HV_EN# (O) ..............................................................................................................................................93
10.1.25 IERR# (O) ..................................................................................................................................................93
10.1.26 IGNNE# (I) ................................................................................................................................................93
10.1.27 INIT# (I) .....................................................................................................................................................93
10.1.28 INTR - see LINT[0] ..................................................................................................................................94
10.1.29 LINT[1:0] (I).............................................................................................................................................94
10.1.30 LOCK# (I/O) .............................................................................................................................................94
10.1.31 L2_SENSE ................................................................................................................................................94
10.1.32 OCVR_EN (I) ............................................................................................................................................94
10.1.33 OCVR_OK(O) ...........................................................................................................................................94
10.1.34 NMI - See LINT[1] ...................................................................................................................................94
10.1.2 A20M# (I) ....................................................................................................................................................89
10.1.3 ADS# (I/O) ...................................................................................................................................................89
10.1.4 AERR# (I/O) ................................................................................................................................................89
10.1.5 AP[1:0]# (I/O) ............................................................................................................................................89
10.1.6 BCLK (I).......................................................................................................................................................90
10.1.7 BERR# (I/O) ................................................................................................................................................90
10.1.8 BINIT# (I/O) ................................................................................................................................................90
10.1.9 BNR# (I/O)...................................................................................................................................................90
10.1.10 BP[3:2]# (I/O) ..........................................................................................................................................90
10.1.11 BPM[1:0]# (I/O) ......................................................................................................................................90
10.1.12 BPRI# (I)....................................................................................................................................................90
10.1.13 BR0# (I/O), BR[3:1]# (I) ........................................................................................................................90
10.1.14 BR0# (I/O), BR[3:1]# (I) ........................................................................................................................91
10.1.15 CORE_AN_SENSE (O) ...........................................................................................................................92
10.1.16 D[63:00]# (I/O) ........................................................................................................................................92
10.1.17 DBSY# (I/O) ..............................................................................................................................................92
10.1.18 DEFER# (I) ...............................................................................................................................................92
10.1.19 DEP[7:0]# (I/O) .......................................................................................................................................92
10.1.20 DRDY# (I/O)..............................................................................................................................................92
10.1.21 FERR# (O) .................................................................................................................................................93
10.1.22 FLUSH# (I)................................................................................................................................................93
10.1.23 HIT# (I/O), HITM# (I/O).........................................................................................................................93
10.1.24 HV_EN# (O) ..............................................................................................................................................93
10.1.25 IERR# (O) ..................................................................................................................................................93
10.1.26 IGNNE# (I) ................................................................................................................................................93
10.1.27 INIT# (I) .....................................................................................................................................................93
10.1.28 INTR - see LINT[0] ..................................................................................................................................94
10.1.29 LINT[1:0] (I).............................................................................................................................................94
10.1.30 LOCK# (I/O) .............................................................................................................................................94
10.1.31 L2_SENSE ................................................................................................................................................94
10.1.32 OCVR_EN (I) ............................................................................................................................................94
10.1.33 OCVR_OK(O) ...........................................................................................................................................94
10.1.34 NMI - See LINT[1] ...................................................................................................................................94