Intel 1.40 GHz RH80532NC017256 Scheda Tecnica

88 Datasheet

 

298517-006 

The EDGCTRLP (Edge Rate Control) signal is used to configure the edge rate of the AGTL output 
buffers. Connect the signal to V

SS

 with a 110-

Ω, 1% resistor.  

The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked floating-
point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and it is included for 
compatibility with systems using DOS-type floating-point error reporting. 

When the FLUSH# (Flush) input signal is asserted, the processor writes back all internal cache lines in 
the Modified state and invalidates all internal cache lines. At the completion of a flush operation, the 
processor issues a Flush Acknowledge transaction. The processor stops caching any new data while the 
FLUSH# signal remains asserted. 

On the active-to-inactive transition of RESET#, each processor bus agent samples FLUSH# to determine 
its power-on configuration.  

The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop operation results, 
and must be connected to the appropriate pins/balls on both agents on the system bus. Either bus agent 
can assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be 
continued by reasserting HIT# and HITM# together. 

The IERR# (Internal Error) signal is asserted by the processor as the result of an internal error. Assertion 
of IERR# is usually accompanied by a SHUTDOWN transaction on the system bus. This transaction 
may optionally be converted to an external error signal (e.g., NMI) by system logic. The processor will 
keep IERR# asserted until it is handled in software or with the assertion of RESET#, BINIT, or INIT#. 

The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to ignore a numeric error 
and continue to execute non-control floating-point instructions. If IGNNE# is deasserted, the processor 
freezes on a non-control floating-point instruction if a previous instruction caused an error. IGNNE# has 
no affect when the NE bit in control register 0 (CR0) is set. 

The INIT# (Initialization) signal is asserted to reset integer registers inside the processor without 
affecting the internal (L1 or L2) caches or the floating-point registers. The processor begins execution at 
the power-on reset vector configured during power-on configuration. The processor continues to handle 
snoop requests during INIT# assertion. INIT# is an asynchronous input. 

If INIT# is sampled active on RESET#'s active-to-inactive transition, then the processor executes its 
built-in self-test (BIST).