Intel III M 866 MHz BXM80530B866512 Scheda Tecnica
Codici prodotto
BXM80530B866512
Mobile Intel
®
Pentium
®
III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,
900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage 700 MHz,
Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz
Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz
44 Datasheet
283653-002
4.
System Signal Simulations
Many scenarios have been simulated to generate a set of GTL+ processor system bus layout
guidelines, which are available in the Mobile Pentium
guidelines, which are available in the Mobile Pentium
®
III Processor GTL+ System Bus Layout
Guideline. Systems must be simulated using the IBIS model to determine if they are compliant
with this specification.
with this specification.
4.1
System Bus Clock (BCLK) and PICCLK AC Signal
Quality Specifications
Quality Specifications
Table 23 and Figure 17 show the signal quality for the system bus clock (BCLK) signal, and Table
24 and Figure 17 show the signal quality for the APIC bus clock (PICCLK) signal at the
processor. BCLK and PICCLK are 2.5V clocks.
24 and Figure 17 show the signal quality for the APIC bus clock (PICCLK) signal at the
processor. BCLK and PICCLK are 2.5V clocks.
Table 23. BCLK Signal Quality Specifications
Symbol Parameter
Min Max Unit Figure
Notes
V1 V
IL,BCLK
0.5
Note
1
V2 V
IH,BCLK
2.0
Note
1
V3 V
IN
Absolute Voltage Range
-0.7
3.5
V
Undershoot/Overshoot,
Note 2
Note 2
V4
BCLK Rising Edge Ringback
2.0
V
Absolute Value, Note 3
V5
BCLK Falling Edge Ringback
0.5
V
Absolute Value, Note 3
NOTES:
1.
The clock must rise/fall monotonically between V
IL,BCLK
and V
IH,BCLK
.
2.
These specifications apply only when BCLK is running, see Table 12 for the DC specifications for when
BCLK is stopped. BCLK may not be above V
BCLK is stopped. BCLK may not be above V
IH,BCLK,max
or below V
IL,
BCLK,min
for more than 50% of the clock
cycle.
3.
The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can go to after passing the V
voltage the BCLK signal can go to after passing the V
IH,BCLK
(rising) or V
IL,BCLK
(falling) voltage limits.
Table 24. PICCLK Signal Quality Specifications
Symbol Parameter
Min
Max Unit
Figure Notes
V1 V
IL25
0.7
V
Figure 17 Note 1
V2 V
IH25
2.0
V
Figure 17 Note 1
V3 V
IN
Absolute Voltage Range
-0.7 3.5
V
Figure 17 Undershoot,Overshoot, Note 2
V4
PICCLK Rising Edge Ringback
2.0
V
Figure 17 Absolute Value, Note 3
V5
PICCLK Falling Edge Ringback
0.7
V
Figure 17 Absolute Value, Note 3
NOTES:
1.
The clock must rise/fall monotonically between V
IL25
and V
IH25
.
2.
These specifications apply only when PICCLK is running, see Table 12 for the DC specifications for when
PICCLK is stopped. PICCLK may not be above V
PICCLK is stopped. PICCLK may not be above V
IH25,max
or below V
IL25,min
for more than 50% of the clock
cycle.
3.
The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the PICCLK signal can go to after passing the V
voltage the PICCLK signal can go to after passing the V
IH25
(rising) or V
IL25
(falling) voltage limits.