Intel 4 HT 631 80552PG0802M2M Scheda Tecnica

Datasheet

65

 

BCLK[1:0]

Input

The differential pair BCLK (Bus Clock) determines the FSB 
frequency. All processor FSB agents must receive these signals to 
drive their outputs and latch their inputs.
All external timing parameters are specified with respect to the 
rising edge of BCLK0 crossing V

CROSS

.

BINIT#

Input/

Output

BINIT# (Bus Initialization) may be observed and driven by all 
processor FSB agents and if used, must connect the appropriate 
pins/lands of all such agents. If the BINIT# driver is enabled during 
power-on configuration, BINIT# is asserted to signal any bus 
condition that prevents reliable future operation.
If BINIT# observation is enabled during power-on configuration, 
and BINIT# is sampled asserted, symmetric agents reset their bus 
LOCK# activity and bus request arbitration state machines. The bus 
agents do not reset their IOQ and transaction tracking state 
machines upon observation of BINIT# activation. Once the BINIT# 
assertion has been observed, the bus agents will re-arbitrate for 
the FSB and attempt completion of their bus queue and IOQ 
entries.
If BINIT# observation is disabled during power-on configuration, a 
central agent may handle an assertion of BINIT# as appropriate to 
the error handling architecture of the system.

BNR#

Input/

Output

BNR# (Block Next Request) is used to assert a bus stall by any bus 
agent unable to accept new bus transactions. During a bus stall, 
the current bus owner cannot issue any new transactions.

BOOTSELECT

Input

This input is required to determine whether the processor is 
installed in a platform that supports the Pentium 4 processor. The 
processor will not operate if this signal is low. This input has a weak 
internal pull-up to V

CC

.

BPM[5:0]#

Input/

Output

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance 
monitor signals. They are outputs from the processor which 
indicate the status of breakpoints and programmable counters used 
for monitoring processor performance. BPM[5:0]# should connect 
the appropriate pins/lands of all processor FSB agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP 
port. PRDY# is a processor output used by debug tools to 
determine processor debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP 
port. PREQ# is used by debug tools to request debug operation of 
the processor.
These signals do not have on-die termination. Refer to 

 for termination requirements.

BPRI#

Input

BPRI# (Bus Priority Request) is used to arbitrate for ownership of 
the processor FSB. It must connect the appropriate pins/lands of all 
processor FSB agents. Observing BPRI# active (as asserted by the 
priority agent) causes all other agents to stop issuing new 
requests, unless such requests are part of an ongoing locked 
operation. The priority agent keeps BPRI# asserted until all of its 
requests are completed, then releases the bus by de-asserting 
BPRI#.