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RJ80535LC0131M
64
Intel
®
Pentium
®
M Processor Datasheet
Package Mechanical Specifications and Pin Information
DPSLP#
Input
DPSLP# when asserted on the platform causes the processor to transition from
the Sleep state to the Deep Sleep state. In order to return to the Sleep state,
DPSLP# must be deasserted. DPSLP# is driven by the ICH4-M component and
also connects to the MCH-M component of the Intel 855PM or Intel 855GM
chipset.
the Sleep state to the Deep Sleep state. In order to return to the Sleep state,
DPSLP# must be deasserted. DPSLP# is driven by the ICH4-M component and
also connects to the MCH-M component of the Intel 855PM or Intel 855GM
chipset.
DPWR#
Input
DPWR# is a control signal from the Intel 855PM and Intel 855GM chipsets used
to reduce power on the Intel Pentium M data bus input buffers.
to reduce power on the Intel Pentium M data bus input buffers.
DRDY#
Input/
Output
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-common clock data transfer,
DRDY# may be deasserted to insert idle clocks. This signal must connect the
appropriate pins of both processor system bus agents.
indicating valid data on the data bus. In a multi-common clock data transfer,
DRDY# may be deasserted to insert idle clocks. This signal must connect the
appropriate pins of both processor system bus agents.
DSTBN[3:0]#
Input/
Output
Data strobe used to latch in D[63:0]#.
DSTBP[3:0]#
Input/
Output
Data strobe used to latch in D[63:0]#.
FERR#/PBE#
Output
FERR# (Floating-point Error)/PBE#(Pending Break Event) is a multiplexed
signal and its meaning is qualified by STPCLK#. When STPCLK# is not
asserted, FERR#/PBE# indicates a floating point when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
Intel 80387 coprocessor, and is included for compatibility with systems using
MS-DOS* type floating-point error reporting. When STPCLK# is asserted, an
assertion of FERR#/PBE# indicates that the processor has a pending break
event waiting for service. The assertion of FERR#/PBE# indicates that the
processor should be returned to the Normal state. When FERR#/PBE# is
asserted, indicating a break event, it will remain asserted until STPCLK# is
deasserted. Assertion of PREQ# when STPCLK# is active will also cause an
FERR# break event. For additional information on the pending break event
functionality, including identification of support for the feature and enable/disable
information, refer to Volume 3 of the Intel
signal and its meaning is qualified by STPCLK#. When STPCLK# is not
asserted, FERR#/PBE# indicates a floating point when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
Intel 80387 coprocessor, and is included for compatibility with systems using
MS-DOS* type floating-point error reporting. When STPCLK# is asserted, an
assertion of FERR#/PBE# indicates that the processor has a pending break
event waiting for service. The assertion of FERR#/PBE# indicates that the
processor should be returned to the Normal state. When FERR#/PBE# is
asserted, indicating a break event, it will remain asserted until STPCLK# is
deasserted. Assertion of PREQ# when STPCLK# is active will also cause an
FERR# break event. For additional information on the pending break event
functionality, including identification of support for the feature and enable/disable
information, refer to Volume 3 of the Intel
Architecture Software Developer’s
Manual
and the Intel
Processor Identification and CPUID Instruction
application note.
For termination requirements please refer to the platform design guides.
GTLREF
Input
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF
should be set at 2/3 V
should be set at 2/3 V
CCP
. GTLREF is used by the AGTL+ receivers to determine
if a signal is a logical 0 or logical 1. Please refer to the platform design guides for
details on GTLREF implementation.
details on GTLREF implementation.
Table 22. Signal Description (Sheet 3 of 7)
Name
Type
Description
Signals
Associated Strobe
D[15:0]#, DINV[0]#
DSTBN[0]#
D[31:16]#, DINV[1]#
DSTBN[1]#
D[47:32]#, DINV[2]#
DSTBN[2]#
D[63:48]#, DINV[3]#
DSTBN[3]#
Signals
Associated Strobe
D[15:0]#, DINV[0]#
DSTBP[0]#
D[31:16]#, DINV[1]#
DSTBP[1]#
D[47:32]#, DINV[2]#
DSTBP[2]#
D[63:48]#, DINV[3]#
DSTBP[3]#