Intel i3-2328M FF8062701275100 Scheda Tecnica
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FF8062701275100
Datasheet, Volume 1
81
Signal Description
6.9
Test Access Points (TAP) Signals
6.10
Error and Thermal Protection Signals
Table 6-11. Test Access Points (TAP) Signals
Signal Name
Description
Direction/
Buffer Type
BPM#[7:0]
Breakpoint and Performance Monitor Signals: These signals are
outputs from the processor that indicate the status of breakpoints
and programmable counters used for monitoring processor
performance.
I/O
CMOS
BCLK_ITP
BCLK_ITP#
These pins are connected in parallel to the top side debug probe to
enable debug capacities.
I
DBR#
DBR# is used only in systems where no debug port is implemented
on the system board. DBR# is used by a debug port interposer so
that an in-target probe can drive system reset.
O
PRDY#
PRDY# is a processor output used by debug tools to determine
processor debug readiness.
O
Asynchronous
CMOS
PREQ#
PREQ# is used by debug tools to request debug operation of the
processor.
I
Asynchronous
CMOS
TCK
TCK (Test Clock): This signal provides the clock input for the
processor Test Bus (also known as the Test Access Port). TCK must be
driven low or allowed to float during power on Reset.
I
CMOS
TDI
TDI (Test Data In): This signal transfers serial test data into the
processor. TDI provides the serial input needed for JTAG specification
support.
I
CMOS
TDO
TDO (Test Data Out): This signal transfers serial test data out of the
processor. TDO provides the serial output needed for JTAG
specification support.
O
Open Drain
TMS
TMS (Test Mode Select): A JTAG specification support signal used by
debug tools.
I
CMOS
TRST#
TRST# (Test Reset): This signal resets the Test Access Port (TAP)
logic. TRST# must be driven low during power on Reset.
I
CMOS
Table 6-12. Error and Thermal Protection Signals (Sheet 1 of 2)
Signal Name
Description
Direction/
Buffer Type
CATERR#
Catastrophic Error: This signal indicates that the system has
experienced a catastrophic error and cannot continue to operate. The
processor will set this for non-recoverable machine check errors or
other unrecoverable internal errors.
On the processor, CATERR# is used for signaling the following types of
On the processor, CATERR# is used for signaling the following types of
errors:
• Legacy MCERRs – CATERR# is asserted for 16 BCLKs.
• Legacy IERRs – CATERR# remains asserted until warm or cold
• Legacy IERRs – CATERR# remains asserted until warm or cold
reset.
O
CMOS
PECI
PECI (Platform Environment Control Interface): A serial sideband
interface to the processor, it is used primarily for thermal, power, and
error management.
I/O
Asynchronous
PROCHOT#
Processor Hot: PROCHOT# goes active when the processor
temperature monitoring sensor(s) detects that the processor has
reached its maximum safe operating temperature. This indicates that
the processor Thermal Control Circuit (TCC) has been activated, if
enabled. This signal can also be driven to the processor to activate the
TCC.
CMOS Input/
Open-Drain
Output