Intel 9560 CM8063101049716 Scheda Tecnica

42

I

CC_CORE

I

CC 

for core

180

A

I

CC_CORE_TDC

Thermal Design Current for Core

131

A

1

1. ICC_CORE_TDC is the sustained (DC equivalent) current that the processor core is capable of drawing indefinitely and should be 

used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for monitoring its 

temperature and asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform the processor 

and platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor. Please see 

the Ararat Voltage Regulator Module Design Guide for further details. The processor is capable of drawing ICC_CORE_TDC 

indefinitely. Refer to 

 for further details on the average processor current draw over various time durations. This 

parameter is based on design characterization and is not tested.

I

CC_CORE_STEP

Max Load step for core

95

A

2

2. During system power on, the pulse inrush (ICC_CORE_STEP) can be as high as 130A peak-to-peak.

d

ICC_CORE/dt

Slew rate for core at Ararat output

154

A/us

I

CC_UNCORE

I

CC 

for uncore

50

A

I

CC_UNCORE_TDC

Thermal Design Current for Uncore

43

A

3

3. ICC_UNCORE_TDC is the sustained (DC equivalent) current that the processor uncore is capable of drawing indefinitely and 

should be used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for 

monitoring its temperature and asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform 

the processor and platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor. 

Please see the Ararat Voltage Regulator Module Design Guide for further details. The processor is capable of drawing 

ICC_UNCORE_TDC indefinitely. This parameter is based on design characterization and is not tested.

I

CC_UNCORE_STEP

Max Load step for uncore

22

A

4

4. During system power on, the pulse inrush (ICC_UNCORE_STEP) can be as high as 40A peak-to-peak.

dI

CC_UNCORE/dt

Slew rate for uncore at Ararat output

75

A/us

I

CC_IO

I

CC 

for processor I/O

22

A

5

5. The ICC_IO current specification applies to the total current from VCCIO pins.

I

CC_Analog

I

CC

 for processor Analog

4

A

I

CC33_SM

I

CC33

 for main supply

200

mA

0.01

100 1000

10

1

0.1

ITDC

IMax

Time Duration (us)

Su

st

ai

ne

d Cu

rr

e

nt (A

)