Intel i5-4200H CL8064701470601 Scheda Tecnica
Codici prodotto
CL8064701470601
10.0
DDR Data Swizzling
The BGA processors do not implement DDR data swizzling.
For rPGA processors, to achieve better memory performance and timing, Intel Design
performed DDR Data pin swizzling that will allow a better use of the product across
different platforms. Swizzling has no effect on functional operation and is invisible to
the operating system/software.
However, during debug, swizzling needs to be taken into consideration. Therefore, this
swizzling information is presented. When placing a DIMM logic analyzer, the design
engineer must pay attention to the swizzling table in order to be able to debug
memory efficiently.
Table 62.
DDR Data Swizzling Table – Channel A
Pin Name
Pin Number
rPGA
MC Pin Name
SA_DQ0
AR15
DQ03
SA_DQ1
AT14
DQ06
SA_DQ2
AM14
DQ04
SA_DQ3
AN14
DQ05
SA_DQ4
AT15
DQ07
SA_DQ5
AR14
DQ02
SA_DQ6
AN15
DQ01
SA_DQ7
AM15
DQ00
SA_DQ8
AM9
DQ15
SA_DQ9
AN9
DQ11
SA_DQ10
AM8
DQ14
SA_DQ11
AN8
DQ10
SA_DQ12
AR9
DQ12
SA_DQ13
AT9
DQ08
SA_DQ14
AR8
DQ13
SA_DQ15
AT8
DQ09
SA_DQ16
AJ9
DQ21
SA_DQ17
AK9
DQ20
SA_DQ18
AJ6
DQ22
SA_DQ19
AK6
DQ23
SA_DQ20
AJ10
DQ17
continued...
Pin Name
Pin Number
rPGA
MC Pin Name
SA_DQ21
AK10
DQ16
SA_DQ22
AJ7
DQ18
SA_DQ23
AK7
DQ19
SA_DQ24
AF4
DQ31
SA_DQ25
AF5
DQ30
SA_DQ26
AF1
DQ27
SA_DQ27
AF2
DQ26
SA_DQ28
AG4
DQ28
SA_DQ29
AG5
DQ29
SA_DQ30
AG1
DQ25
SA_DQ31
AG2
DQ24
SA_DQ32
J1
DQ32
SA_DQ33
J2
DQ33
SA_DQ34
J5
DQ34
SA_DQ35
H5
DQ38
SA_DQ36
H2
DQ37
SA_DQ37
H1
DQ36
SA_DQ38
J4
DQ35
SA_DQ39
H4
DQ39
SA_DQ40
F2
DQ41
SA_DQ41
F1
DQ40
continued...
DDR Data Swizzling—Processor
Mobile 4th Generation Intel
®
Core
™
Processor Family, Mobile Intel
®
Pentium
®
Processor Family, and Mobile Intel
®
Celeron
®
Processor Family
July 2014
Datasheet – Volume 1 of 2
Order No.: 328901-007
135