Intel i5-4200H CL8064701470601 Scheda Tecnica

This chapter describes the processor signals. The signals are arranged in functional

groups according to the associated interface or category. The following notations are

used to describe the signal type.

I

Input pin

O

Output pin

I/O

Bi-directional Input/Output pin

The signal description also includes the type of buffer used for the particular signal

(see the following table).

PCI Express*

PCI Express* interface signals. These signals are compatible with PCI Express 3.0

Signaling Environment AC Specifications and are AC coupled. The buffers are not 3.3 V-

tolerant. See the PCI Express Base Specification 3.0.

eDP

Embedded Display Port interface signals. These signals are compatible with VESA Rev 1.3

eDP specifications and the interface is AC coupled. The buffers are not 3.3V- tolerant.

FDI

Intel Flexible Display interface signals. These signals are based on PCI Express 2.0

Signaling Environment AC Specifications (2.7 GT/s), but are DC coupled. The buffers are

not 3.3 V- tolerant.

DMI

Direct Media Interface signals. These signals are compatible with PCI Express 2.0

Signaling Environment AC Specifications, but are DC coupled. The buffers are not 3.3 V-

tolerant.

CMOS

CMOS buffers. 1.05V- tolerant

DDR3L/DDR3L-

RS

DDR3L/DDR3L-RS buffers: 1.35 V- tolerant

A

Analog reference or output. May be used as a threshold voltage or for buffer

compensation

GTL

Gunning Transceiver Logic signaling technology

Ref

Voltage reference signal

Asynchronous 

1

Signal has no timing relationship with any reference clock.

1. Qualifier for a buffer type.

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

July 2014

Datasheet – Volume 1 of 2

Order No.: 328901-007

83