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FH8065401488915
Volume 2—SMBus 2.0 Unit 1 - Host—C2000 Product Family
Controller Characteristics and Operation
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
324
Order Number: 330061-002US
Table 15-19. Target Header Encodings (TSTS) Per Transaction Type (TTYPE) (Sheet 1 of 2)
TTYPE
Cycle
Type
TSTS
0000
Success
TSTS 0001
PEC Error
TSTS
0010
Protocol Error
TSTS
0011
Hardware NACK
TSTS
0100
External
NACK
TSTS
0101
Clock Low
Time Out
TSTS
0110
Data Low
Time Out
0101
GP Block
GP Block
Read
No
errors
N/A (the
hardware
transmits the
PEC)
• A collision is
detected by the
hardware. This
happens when
the hardware
intended to drive
NACK and saw
an ACK on the
bus.
• The external
master signals
stop/restart,
etc. in the
middle of a byte.
• The external
master signals
stop on a byte
boundary before
the byte count
expired.
• The external
master
continues
driving more
clocks even after
the hardware
has provided all
the bytes.
• The external
master drives
ACK instead of
NACK on the
PEC byte sent by
the hardware.
• Bits [7:1] of the
repeated start
address do not
match the GPBR
address.
• Bit 0 of the
repeated start
address is 0,
and the policy is
to check for 1.
Command code
byte received from
the external master
does not match the
expected value.
The external
master
NACKs at
least one of
the bytes
provided by
the
hardware,
i.e.,
Byte Count,
Byte Count,
Data1,
Data2,
Data3,...,
DataN.
The hardware
detects the
SMBus clock
low time-out
anywhere in
the middle of
the
transaction
that it is
actively
servicing.
The
hardware
detects the
SMBus data
low time-out
anywhere in
the middle of
the
transaction
that it is
actively
servicing.