Intel C2518 FH8065501516710 Scheda Tecnica

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

387

Byte Count (N)

0x01...N

SoC

N = 0x01 for Busy State:

• Byte 1 = 0x01 (CMD_BUSY bit set)

N = 0x02 for Transaction Errors

• Byte 1 = 0x02 (CMD_ERR bit set)
• Byte 2 = Error code

N > 2 indicates the request PECI command 

executed successfully:

• Byte 1 = 0x0
• Byte 2 = 0x0
• Byte [N:3] = PECI response data

Byte 1

Control 

Data

Status Byte (CMD_STAT):
Bits [7:2] = Reserved
Bit 1 = CMD_ERR

• This bit is set by the SoC if the PECI proxy 

interface detects Transaction Error. The 

Error Code is defined in Byte 2.

Bit 0 = CMD_BUSY

• This bit is set by the SoC while a PECI 

command is executing. It is reset by the 

SoC when the PECI command operation is 

completed.

Byte 2

Control 

Data

Error Code (ERR_CODE):
0x00 = PECI_ST_OK

• PECI command completed successfully

0x01 = PECI_ST_BAD_FORMAT

• SMBus PECI message incorrectly formatted

0x09 = PECI_ST_DISABLED

• PECI driver disabled

0x3E = PECI_INVALID_SOCKET

• Invalid PECI socket number

0xE1 = PECI_ST_TRANS_TIMEOUT_ERROR

• PECI Transaction Time-out (e.g., PECI 

Controller not responding to commands or 

hangs)

0xFE = PECI_ST_FAILURE

• General PECI Failure

0xFF = PECI_ST_UNKNOWN

• Unknown Status

0x02 = PECI_ST_FCS_REQ_ERROR

• Error in PECI Request FCS

0x04 = PECI_ST_FCS_RSP_ERROR

• Error in PECI Response FCS

0x08 = PECI_ST_LINK_ERROR

• PECI Link Error

Byte [N:3]

PECI 

Response 

Data

PECI Response Data:
PECI Response Data as described for each PECI 

command in the PECI Specification. It contains 

all data returned by the PECI client that resides 

between the Write FCS byte and Read FCS 

byte.
These bytes are valid only when the PECI 

command completes successfully and the 

CMD_ERR bit in the Status Byte (Byte 1; 

Bit[1]) is cleared.