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FH8065401488914
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
137
Volume 2—SoC Reset and Power Supply Sequences—C2000 Product Family
Reset Sequences and Power-Down Sequences
Figure 7-5. S5 State to S0 State Sequence - Cold Reset
These SoC inputs are
in the de-asserted
state during entire
period: RTEST_B
SRTCRST_B
RSMRST_B
SoC output:
SUSPWRDNACK
RTC power well and SUS power well
voltages are valid during this entire period
VDDQ voltage group ramps-up
and becomes valid
SoC output:
PMU_SLP_S3_B
SoC output:
PMU_SLP_DDRVTT_B
SoC inputs:
DDR3_0_DRAM_PWROK
DDR3_1_DRAM_PWROK
SoC output:
PMU_PLTRST_B
All DDR3 and Core
Voltages Valid and all
Reference Clocks stable at
SoC input pins
SoC output:
SUS_STAT_B
SoC output:
CPU_RESET_B
t
33
t
35
Core Voltage supply
sequencing may start
anytime after here.
See text.
SoC input:
COREPWROK
SoC inputs:
DDR3_0_VCCA_PWROK
DDR3_1_VCCA_PWROK
SoC De-glitch Filter
t
34
SoC output:
PMU_SLP_S45_B